The Threat That Just Keeps Getting Bigger: DRAM Row Hammer
Who is to blame for DDR Memory ECC errors?
What do you mean there is NO Validation Report?
In our Services department we see all sorts of systems, network switches, routers, and medical devices, etc. They all share a common theme….the DDR Memory does not work right. The engineers sending us these problem systems are frustrated and we ...
Want to Ca$h in on Bitcoin, BlockChain and Cryptocurrency? Speed up your DDR Memory Accesses
Fast 3200MT/s DDR4 SODIMMs
FAST SODIMMS for DDR4 are here!
Is your DDR4 Memory Controller Compliant?
Finally! After 2 ½ years FuturePlus Systems was successful in sponsoring JEDEC’s first document on protocol checks, JEP175 DDR4 Protocol Checks. But we didn’t do it alone! Many thanks to the other Test and Measurement vendors, EDA vendors and ...
Critical Memory Performance Metrics for DDR4 Systems: Page Hit Analysis
Page Hit and Miss is often a metric used to describe caching architectures. In this context a Hit is when the page was already open and the Read/Write transaction occurred. A Miss is when an Activate[1] had to occur just prior in order to open the ...