Memory Analysis for High Performance Applications
This Testing is available for DDR4 DIMM/SODIMM or embedded applications (memory down). This analysis is ideal for any application where memory performance is critical:
- High Frequency Trading
- Bitcoin Mining
- CryptoCurrency Mining
- DLT or Distributed Ledger Technology
- BlockChain applications
- Power Management
- Data base lookup
- Image recognition
- Artificial Intelligence
- Machine Learning
Only available at FuturePlus Systems this unique analysis is done in system, right at the hardware level. A complete report with the following metrics are part of the service offered.
- Margin Testing Identifies Key Latency Parameters
- Command Bus Utilization Analysis
- Bus Modes Analysis
- Power Management Analysis
- Data Bus Utilization Analysis
- Page Hit Analysis
- Multiple Open Banks Analysis
- Bank Group Analysis
- Bank Utilization Analysis
- Summary Modes that show performance over long periods of time
Margin Testing Identifies Key Latency Parameters
Per the JEDEC Specification the distance in time between two transactions on the DDR4 bus cannot be too close together or too far apart. If the memory controller puts commands too close together the DRAM will not have time to respond and data corruption can occur. Conversely, if the transactions are too far apart it can mean that the memory controller is inefficient, or a BIOS programming error has occurred. In any event for Performance you want the latencies to be as short as possible without violating the specification. The BIOS and the Memory Controller working together read the SPD of the DIMM/SODIMM and determine the correct settings. In many cases these are not correct due to the large number of possibilities and the differences in various motherboards. This analysis will alert you to those latencies that can be improved and if any settings are leading to JEDEC specification violations.
Command Bus Utilization Analysis
This covers all DDR4 commands (24 specific types), broken down by Rank and Bank and by channel. The display will display rates (events per second) or percentages (used cycles versus total cycles, or versus CKE qualified cycles) of any command types. This is very useful for giving an overview of all of the traffic on the DR4 Memory bus.
Bus Modes Analysis
This covers 11 different DDR4 modes, plus clock stop times, broken down by Rank. Includes the following bus states or modes: Reset, Idle, Active, Precharge Power Down, Active Power Down, Maximum Power Down Mode, Self-Refresh, DLL Disable, Write Leveling, MPR Mode (AKA Read leveling or Read training), and VREF Training Mode. The display can show the Amount of Time spent in each mode as Time (time per second) or percentages (used time versus Elapsed time).
Power Management Analysis
This collects all the power related information in one place: Refresh, SRE, SRX, Prech PDE, Active PDE, PDX commands, Idle, Active, Prech PD, Active PD, Self Refresh, Deep Power Down and DLL Disable. The display can calculate and show rates (events per second) or percentages (used cycles versus total cycles, or versus CKE qualified cycles) and can break down these numbers on a Channel, Slot, or Rank basis. The display can show Amount of Time spent in each mode, as Times (time per second) or percentages (used time versus Elapsed time) and can break down these numbers on a Rank basis.
Data Bus Utilization Analysis
Data bus utilizations can be expressed as rates (MB Per Sec) or as percentages (used cycles versus total cycles, or versus CKE qualified cycles) and these can be broken down on a per-direction (read/write), per-channel, per-Rank, or Per-Bank basis. OTF (on the fly) is handled properly in the calculations.
Page Hit Analysis
Hits, Misses and Unused Pages are detected. This can be broken down on a per-direction (read or write), per-Channel, per-Rank or per-Bank basis. This is analogous to cache hit/miss however with a bit of a twist. A HIT is when the page is already open when the Read/Write is issued. A MISS is when the Memory Controller must do an ACTIVATE Command ahead of time in order to open the bank. An unused is when the Memory Controller ‘guesses wrong’ in anticipation of using the bank and opens a bank and then closes it without an access.
Multiple Open Banks Analysis
This analysis counts the amount of time that specific numbers of banks are open simultaneously, and works through bus Active, and Active Power-Down modes of bus operation. The display can show total times (total states per second) or percentages (used states versus elapsed time), and can break down these numbers on a Channel, Slot or Rank basis. Having lots of banks open at the same time is great for performance (see Page Hit Analysis) since it is more likely that the bank will be open when the Read/Write command is issued but is bad for Power Management as open banks burn power.
Bank Utilization Analysis
The display can show the Amount of Time or Cycles (per second) that each bank is Active (or conversely, as Precharged), or as percentages (Active time versus Elapsed time, or Active Cycles versus Qualified Cycles), and can break down these numbers on a Rank basis. This metric is useful for determining if there is a ‘party at bank 5’ for example in that a disproportionate amount of traffic is headed to a single bank (or location). This can be a sign of a potential ‘Row Hammer’ attack or other Denial of Service activity. In addition this could indicate that software is spinning on a semaphore which would indicate that the workload is stalled for some reason.
Bank Group Analysis
This analysis looks at consecutive Read/Write operations to see how many stay within the Bank Group, which is favored, for performance. The display can calculate and show rates (events per second) or percentages (counts in one category vs the sum of counts in all categories) and can break down these numbers on a Channel, Slot, or Rank basis. The 8 categories are:
- RD to RD same group, RD to WR same group, WR to WR same group, WR to RD same group
- RD to RD different group, RD to WR different group, WR to WR different group, WR to RD different group
The old saying ‘Time is money’ could not be a more true statement when it comes to high speed DDR Memory accesses. If you have critical applications this analysis will give you insight into where you can make changes and if one system is better than another for your particular workload.
In addition our memory audit can also increase performance by looking for error situations which can cause system crashes or retries at the higher software level. Both of these in-depth analysis services are unique to FuturePlus Systems. Contact us for a quote today!