Attention all Bit Coin, Ethereum Miners, Block Chain Fans and Distributed Ledger Technology experts. Do you REALLY understand the computing limits of your hardware? These applications are among the most compute intensive applications today. Like most compute intensive applications DDR Memory is involved.
There is some confusion over memory bandwidth versus memory latency. Latency is the time to first access. See below examples of a memory subsystem running well below the minimum latency allowed by the JEDEC DDR4 specification for some parameters. Identifying these bottle necks can dramatically increase your memory access time thus your mining application. Tuning your system for minimum latencies can add $$ to your crypto wallet.
Figure 1: DDR4 Memory Latencies measured on every clock cycle continuously. Measurement made by the DDR Detective from FuturePlus Systems
Bandwidth on the other hand is the amount of data that can be transferred over a certain time. This is the Mega Bytes per Second metric. See below. This metric is important as it determines the amount of data bandwidth that can be sustained over a longer period of time. If your latency can be improved this number will also improve.
Figure 2: DDR4 Memory Bandwidth measured on every clock cycle continuously on a per bank per rank basis. Measurement made by the DDR Detective from FuturePlus Systems
If your mining hardware is using the latest DDR4 Memory there is another metric (over DDR3) that needs to be considered. That is Bank Group tuning. In DDR4, back to back transactions to the same Bank Group, results in a performance penalty. Back to back accesses to different Bank Groups is the performance path. So how is your ASIC or GPU hardware setup? See below a real time chart showing what the back to back accesses look like. Making this measurement is easy…well if you know what your doing and you have the right equipment (spoiler alert! We can help).
Figure 3: DDR4 Bank Group back to back accesses measured on every clock cycle continuously. Measurement made by the DDR Detective from FuturePlus Systems.
Most miners understand the concept of a cache miss and a cache hit. We have a similar metric when it comes to DDR Memory. If a bank is open (previously been opened with an ACTIVATE command) and an access is made we call that a HIT. However if the memory controller has to do the ACTIVATE command first…well you will wait….we call that a MISS. Check out what this looks like on a real system.
Figure 4: DDR4 Page Hit analysis measured on every clock cycle continuously. Measurement made by the DDR Detective from FuturePlus Systems.
Note the ‘unused’. This is caused by the processor ‘guessing’ where the next access is going and opening the bank in anticipation of the access (Think SPECTRE bug). This is a power and bus bandwidth waster when the guess is wrong. The bank then has to be closed so both the OPEN and the CLOSE commands on the DDR4 bus added no value.
Most miners do not want to MISS as that is a performance penalty. So in order to guarantee a HIT the memory controller will open all the banks and leave them open. Now this is a power penalty (hence the reason why mining is power intensive) so understanding what locations in memory your hardware is accessing is key to ensuring the proper power/performance trade off. The graphic below shows a real system with all banks being monitored in real time (NEVER MISSING A CLOCK CYCLE).
Cryptocurrency Mining can be a lucrative endeavor. By closely examining your DDR Memory performance you can add $$ to your wallets. FuturePlus Systems has over 20 years of experience and can give your system the ‘audit’ it needs to make sure you are getting the best use of your mining hardware.
Don’t want to invest in owning your own testing hardware? Let us do the testing for you!