JEDEC’s DDR5 Announcement certainly came as no surprise to those of us working on the standard behind the scenes. The new 5th generation memory bus will have two, 32 bit channels complete with its own Address/Command and Control signals. ECC and CRC will be part of the error checking protocol. This is the first time in the DDR Memory line of standards that will put 2 channels on a single DIMM. Why go to a 32 bit bus? On DDR4 if the slot was in REFRESH, ZQCAL or other ‘stalled’ state the entire RANK was off line to memory traffic. By having a separate channel the Memory Controller can time the maintenance commands to always have some memory available. The increase in burst length to 16 will give the missing bandwidth of going from a 64 bit bus down to a 32 bit bus.
The big news on DDR5 is the double data rate nature of the Address/Command and Control bus. In order to keep the DIMM pin count to the 288, which is what we have for DDR4, the number of pins dedicated to the Address/Command/Control needed to be reduced. So the commands are passed on both the rising and falling edges of the clock. The Address is also handled the same way so it can take 4 clock edges, 2 clock cycles, to pass a command and associated address. Although the host bus will be double data rate on the Address/Command/Control the DRAM part itself will be single data rate. The RCD will handle the conversion. There is also an option for single data rate Address/Command/Control and we will see that on UDIMM implementations. Which brings us to another surprise with DDR5, the UDIMM pinout will be different than the RDIMM/LRDIMM pinout. OUCH!

So why move to DDR5? Good Question! The jury is still out as to what the actual performance improvements will be. Certainly there will be power management improvements but given the complete redesign required it remains to be seen if the investment will pay off.

DDR5 is an evolutionary approach to continuing the DDR paradigm of main memory architecture. Does the industry need to take a fresh look at computer architecture? YES! It appears I am not alone in my thinking as we see CAPI, Gen Z and CCIX all hoping to provide the path beyond the current host memory paradigm dominated by the DDR Standards.

We here at FuturePlus will be ready for this new standard with test equipment that gets DDR5 designs working fast. Currently everything is hush hush so if you would like to hear more contact me! Barb.Aichinger@FuturePlus.com

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