Finally! After 2 ½ years FuturePlus Systems was successful in sponsoring JEDEC’s first document on protocol checks, JEP175 DDR4 Protocol Checks. But we didn’t do it alone! Many thanks to the other Test and Measurement vendors, EDA vendors and Silicon vendors who took the time to review, comment and contribute. This document was driven by the need to standardize the rules behind a memory controller’s accesses to the DDR4 DRAM. Absent the Alert signal, which only asserts for Address/Command Parity or CRC errors, the DRAM has no way to tell the Memory Controller ‘hey you just did an incorrect command sequence or you violated command timing’. The result of incorrect accesses may not be apparent immediately as that location or adjacent locations may not be accessed right away. The result can be data corruption.
The document is the WHAT not the HOW as these measurements can be made with a
Logic Analyzer, Mixed Signal Oscilloscope, Protocol Analyzer (think DDR Detective) or implemented as part of a simulation test bench. The figure below gives a quick overview of how the Protocol Checks are defined in the new JEP175 DDR4 Protocol Checks Document.
JEP175 JEDEC DDR4 Protocol ChecksFigure courtesy of FuturePlus Systems
There are dozens of checks defined in the document but they are in no way the definitive list of ALL possible DDR4 Protocol Checks. We had to start somewhere so this is the list that was agreed upon. In order to assist in plugging in all the defined values for the various DDR4 B speed bins (1600, 1866, 2133, 2400, 2933 and 3200, MT/s) FuturePlus Systems has gone one step further and created a spreadsheet that contains all the equations and their variables across all speedbins.
Figure courtesy of FuturePlus Systems
Need a copy of this spreadsheet? Request one here!
If you are wondering if your DDR4 memory subsystem is violating the DDR4 spec, we can help. Check out our DDR Detective, our logic analyzer interposers and our services. If its DDR Memory FuturePlus has the solution!
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