The JEDEC JC42.3 committees have issued the B version of the DDR4 specification. This version is several years in the making as the original JESD 79-4 DDR4 SDRAM specification was released in September 2012 and the A version published in November of 2013. Those of us in JEDEC have been using the task group version of this spec for several years, finally it is available to non JEDEC members. So what is new and exciting about this B revision? Let’s take a look!
A X32 ballout was added so we can get a 32 bit bus in a single package. Provisions were also added for a 2 die stack in this configuration.
Several changes to make things clearer. This is in response to ambiguities and misunderstandings that have happened over the years with the A version
Single Rank Dual Die per package
This specifies how to put 2 x8 die to create a x16 configuration. 8GB,16GB and 32GB addressing was also specified.
Targeted Row Refresh
Contrary to popular belief TRR is NOT in the final B version. It was for a while, but then removed. Originally, this was in response to the Row Hammer issues of DDR3. Looks like the DRAM vendors found another way to reduce RH failures for DDR4 other than making the Memory Controller babysit frequently accessed Rows. DDR4 does exhibit fewer Row Hammer failures….but it still has some Row Hammer failures (that’s a whole different article!)
Although there is a separate specification for 3DS, the B version does add additional CAS/CW latencies for 3DS.
Post Package Repair
This is enabled/disabled in the Mode Registers and allows systems to actually ‘repair’ failing Rows. Pretty cool! So if you do have a bad Row the DRAM can choose a spare Row to replace the failed row. This feature is optional for 4G devices but required for 8G devices and above. 1 Row per bank group can be repaired with hPPR (hard post package repair).
Soft versus Hard Post Package Repair
Hard PRR takes a bit longer to do but will last between reboots. Soft Post Package Repair will not survive a power cycle.
MAC added to the MPR (Multi Purpose Registers)
Maximum Activation Count. More Row Hammer fallout. DRAM vendors are protecting themselves by specifying that the memory controller cannot do more than the MAC number of ACT commands to a single Row address during a retention cycle. There are several problems with this. There is no way for the memory controller to have a unique counter for the over 4 million unique row addresses for every DRAM in the system. In addition, the memory controller has no idea when the DRAMs 64ms retention cycle starts and stops.
Differential Input Cross voltage
Although the majority of the signals on DDR4 are single ended, the clock and strobe signals are differential. A new section in the B spec gives definition to the voltage at which the strobes cross at the ball of the DRAM. Another new section on Differential Slew Rates was also added to facilitate the above.
New Speed Bin Tables for 2666MT/s to 3200MT/s
Although technically part of the A spec, the B version does a good job specifying the data rates of 2666MT/s-3200MT/s by specifying the timing values needed to operate at those frequencies. This takes us right up to the start of DDR5.
Input Clock Frequency Change
Taking a page from the LPDDR4 playbook the server folks wanted a method for lowering the clock rate in order to save power. They got a much cleaner, more concise method in the B version of the spec.
More definition around normal and extended operating modes
This gives clarity so that vendors can use DRAMs in harsher environments.
VREFDQ Calibration Mode
Clarity and additional timing diagrams and even a script to help folks who design memory controllers to properly train and bring up the DRAM during initialization. Failure to get this right will result in a no-boot.
This mode allows the DRAM to adjust its internal clock to ½ mode or ¼ mode operation. Not supported for data rates below 2666MT/s. Gear Down mode is only supported during initialization and self refresh exit. The B spec gives more clarity and definition.
CAL: Command Address Latency
Although defined in the A spec, more definition and clarity are added in the B spec. Command Address Latency is where the Chip Select asserts several clock cycles before the command/address is valid. This is in contrast to having the command/address coincident with the assertion of Chip Select.
Slight changes to the Read and Write preamble. This is how many clocks will the strobe signals be asserted for prior to the sourcing of the Read or Write data.
Definition of Data Valid Window
YAY! Must have been a test engineer that got this one in. The definition is now clearer and it states that it will be “characterized and guaranteed by design.”
Measurement definitions for timing parameters and a method for calculating differential pulse widths.
New Timing parameters for minimum Read to Write and Write to Read same and different bank group. In the past this has been tCCD, however the B spec now adds more granularity to the spacing between commands.
New section on Write Timing Violations
The B spec carries a stern warning about Write timing Violations. Stating that “if Write timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure that the DRAM works properly.” The DRAM device has only one error pin and it is only for CRC errors and Address/Command parity errors. There is no way for the DRAM to tell the memory controller ‘hey you just did the wrong command sequence or timing access to me’. This is one reason why compliance testing of the protocol and timing is an extremely important step in design verification. The result of subtle timing violations may not be seen in all parts. When it does show up, it can result in undetected data corruption.
Command Address Parity
Although rarely implemented, more definition around operation with Command Address Parity mode was added to the B spec.
Connectivity Test Mode
A JTAG type operation in the B spec gives a much needed definition for this mode. It defines the inputs and what equations correspond to the outputs while in this mode. In addition to input voltage levels and slew rates
A subject near and dear to my heart….the ever popular rounding algorithm. Many parameters in the DDR4 spec are listed in ns. Given that a memory controller is a synchronous device it will issue commands based on clock cycles. In order to make any type of measurement the ns need to be converted to clock cycles. As a non integer result is often to be had a rounding methodology needed to be addressed. Now rounding is not new to DDR as a rounding algorithm has been listed in the SPD spec for years. However it was not clear which parameters it applied to. After some considerable debate the SPD rounding algorithm with the 2.5% guardband was adopted. HOWEVER, once committee members realized that several rounded numbers could be added up to determine a timing parameter, and this small change could result in a 2 clock tic difference, all hell broke loose! Parameters that were being tested for now had to be changed and with the guardband, resulting parameters meant a faster performance requirement. So another ballot was passed to keep the simple roundup for the non-SPD parameters and the 2.5% guardband for just the SPD parameters. HOWEVER, this second ballot never made it into the final draft (I do not know why) and the published B spec has only the 2.5% guardband method. So there you have it! The Rev B DDR4 spec has some latency improvements just due to rounding!
Should we expect a C version? I think so…given that I counted over 200 TBD’s in the spec I think we will continue to see some tweaking which will result in an updated version over the next few years.
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