DDR3 and DDR4 DIMM/SODIMM Testing
FuturePlus Systems will use its extensive cache of test equipment, experience and know how to perform system level tests on DDR3 and DDR4 DIMM and/or SODIMM modules.
DDR3 and DDR4 DIMM and SODIMM Audit: This testing is referred to as an Audit. It does not replace in depth design validation by a design team but rather this testing is a verification that is used for:
- An independent check to ensure operational integrity
- Spot check manufacturing to ensure quality
- Test failing DIMMs/SODIMMs returned from the field to isolate root cause of the failure
Procedure: This testing will be broken into four parts. Mechanical Audit, Electrical Audit, Data Sheet and SPD Audit and then an extensive Row Hammer testing.
Mechanical Audit: This testing will make sure the DIMM/SODIMM module conforms mechanically to the JEDEC MO-309C (DDR4) MO- 269 (DDR3) specification. All of the mechanical parameters such as length, height, gold finger dimensions, notch location and other mechanical attributes that could cause the DIMM or SODIMM to not sit property in the connector are measured and recorded.
Electrical Audit: This testing will be a qualitative measurement. This ensures that a validation has been done and that the signals at the DDR DIMM connector are acceptable with regards to signal swing, alignment, data valid eye size and that none of the strobe signals, data signals, address, command or control signals look appreciably degraded with respect to their form or function. This is not meant to replace a robust design validation. The Keysight logic analyzer and FuturePlus interposer will be used to perform the testing.
Data Sheet and SPD Audit: This test procedure will run the DIMM in a motherboard and vary the latencies and other variable parameters to ensure that the DIMM operates as dictated by its speed bin in a live system. The contents of the SPD will be verified against the latest JEDEC SPD specification.
Row Hammer Audit: FuturePlus System will run Memesis from ThirdIO that will target the DIMM under test with excessive ACTIVATE Commands along with READs and WRITEs to single row addresses. This is known in the industry as the Row Hammer test since a single row is being ‘hammered’ with ACT commands. As geometries shrink and capacities increase DDR Memory cells are susceptible to leakage current from adjacent cells. In the case of DDR Memory a row subjected to excessive ACTIVATE commands can leak current into adjacent row. This row is referred to as the ‘aggressor’. If the adjacent rows, called the ‘victim’ rows, are on the tail end of the cyclical refresh cycle their charge is low. Thus they are susceptible to leakage current that can cause a bit flip. The failure of the DDR Memory cell to hold its charge due to leakage current from an adjacent row when the adjacent row is targeted with excessive ACTIVATE commands is referred to as a Row Hammer failure. The FuturePlus DDR Detective can identify the hammered row address using its Row Hammer detection tool for DDR3 and by using the FS2800 DDR Detective® Performance Counters for DDR4. If Memesis finds a Row Hammer Failure a report will be generated.
The following documents will be created and sent to the customer for each DIMM tested.
- Mechanical Measurement Report
- Eye Scan results with ‘eye’ for each signal
- Burst Scan for each byte (including check bits) for both Reads and Writes
- DDR Detective Command Occurrence Report
- SPD Report
- Row Hammer Testing Results
FuturePlus Systems DIMM and SODIMM Testing Services can be used to find problems in manufacturing, help diagnose failed DIMMs/SODIMMs that come back from the field or just as a general audit to ensure quality.
Let 20+ years of DDR Memory Expertise, using the latest state of the art test equipment help make your company successful!