FS2700 DDR5 Sideband Bus Protocol Analyzer

The FS27xx DDR5 Sideband Bus Protocol Analyzer is the latest DDR5 tool from FuturePlus Systems.  FuturePlus has taken the complexity of 8 different JEDEC specifications and ported them into this very useful tool.  DDR5 Validation Engineers and system integrators will not have to comb through complex specifications defining thousands of bits and register addresses.  The tool takes care of this.  Please request our data sheet for more information.

DDR5 Sideband Bus Features

  • It has two modes of operation:  As Logic Analyzer interface (FS2510) and standalone that runs off the PC via USB (FS2700).  The FS2520 combines both of these features into a single unit.
  • Follows the system at power on from I2C to the I3C transition never missing any traffic
  • Signals can be probed from anywhere on the motherboard or at the DDR5 DIMM/SODIMM
  • Hundreds of registers with thousands of bit settings decoded for your convenience
  • Supports all the Devices/Functions on a DDR5 RDIMM/LRDIMM/SODIMM/UDIMM
  • The latest set of Device/Function registers are always available

DDR5 Sideband Bus Configuration

  • PC Requirements: Windows 10 PC with USB
  • FS2710/FS2720 Keysight Logic Analyzer requirements:
    • 1 M9505A five-slot AXle chassis
    • 1 U4164A Logic Analyzer Modules
    • 1 U4201A cable

DDR5 Sideband Bus: Standalone Protocol Analyzer

  • Two Levels of Triggering
  • Trig Out
  • Storage qualification capture on any slot, function and even register address

Standalone Triggering Features 

  • Trigger on any I3C command
  • Trigger on traffic to any slot or function (ex. Slot 0 RCD or Slot 2 PMIC)
  • Trigger on any Read or Write to a specific slot and function via register address

Standalone Storing Qualification Benefits

  • Store only traffic of interest
  • Store only Traffic to a particular slot or function (ex. All traffic to Temperature Sensor slot 1)
  • Store all traffic to a particular function (ex. both RCD’s on a channel)

DDR5 Sideband Bus Logic Analyzer Preprocessor

  • One POD to the U4164A
  • A single machine with its own clock run in State mode
  • Traditional Inverse assembler with register decode
  • Serial to Parallel conversion with all command codes and data
  • Easy Triggering and store qualification on the Logic Analyzer
  • Correlate with DDR5 bus traffic from FuturePlus slot interposers

DDR5 Sideband Bus Probing

Flex Tip

  • From DDR5 DIMM
  • Anywhere SDA/SCL is located on the motherboard

DDR5 Sideband Bus: Ordering Information

  • FS2700 DDR5 JEDEC Sideband Bus Protocol Analyzer
  • FS2710 DDR5 JEDEC Sideband Bus Preprocessor for the Keysight U4164A
  • FS2720 DDR5 JEDEC Sideband Bus Protocol Analyzer and Preprocessor
FS2700
FS2710/FS2720
Request More Information/Quote or Call: (603) 472-5905
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Request More Information/Quote or Call: (603) 472-5905
Send