Page Hit and Miss is often a metric used to describe caching architectures.  In this context a Hit is when the page was already open and the Read/Write transaction occurred.  A Miss is when an Activate[1] had to occur just prior in order to open the page.  Opening a page takes time and burns power.  An Unused is when the page was opened and then closed with no transaction targeting it.  Memory Controllers use various locality of data algorithms to keep pages open to improve performance.  That is, they open pages ahead of time in order to improve Hit rate.  If they guess wrong and a page was not needed it ends up being closed without being used.  This not only hurts performance because it takes time to open and close pages, but it wastes power as an open page burns more than a closed one.   To gain maximum insight this should be broken down on a per-direction (Read or Write), per-Channel, per-Rank or per-Bank basis.  Below is an example measurement of this metric.

Main Memory Page Hit Analysis

DDR4 Main Memory Page Hit Analysis

[1] Per the JEDEC DDR4 standard an Activate command opens a row (also referred to as a page) and a Precharge command closes it.

WHY Measure this?

  • A page is an allocated space in memory that the controller must ‘open’ prior to reading or writing to.  If pages are allocated and never used performance and power is wasted.  Measuring this gives insight into various page allocation algorithms.
  • Software targeting different applications can act very differently with regards to memory page allocation. By understanding this metric different memory architectures and software can be designed for a better performance match.
  • To compare various memory controller/DRAM designs to see which one runs faster with various software applications


Understanding the Page Open/Page Closed policy of the memory controller for various workloads can give to rise to optimizing the hardware for various workloads.  This will become a more important issue in the future as hardware configurable servers become reality.

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