Row Hammer. The problem no DRAM vendor wants to talk about, except for one, Zentel

Zentel’s new DDR3 DRAM has published data showing zero Row Hammer failures.  I fondly recall talking to a large vendor’s ‘tiger team’ concerning Row Hammer failures a few years back.  I asked them what should their DDR3 users do if they start to experience Row Hammer failures.  Their response? ‘Upgrade to DDR4!’.  ‘How convenient’ I responded, ‘forcing the industry to throw away all those DDR3 based systems so you can sell more DDR4’.  And come to find out, DDR4 although a bit better, still experienced Row Hammer failures! We here at FuturePlus Systems are glad to see our colleagues in academia are still hunting down those Row Hammer vulnerabilities (https://rambleed.com/).  They can feel good about causing the industry to look for solutions, and it appears that Zentel has answered the call. To the best of our knowledge Zentel has the ONLY Row Hammer hardened DDR3 memory on the market.  See the Zentel data sheets here.  #rowhammer, #DDR3, #JEDEC, #AP Memory,...

LPDDR5 vs LPDDR4: What’s the difference?

Recently JEDEC announced the new JESD209-5 Low Power Double Data Rate 5 (LPDDR5) specification.  LPDDR5 is faster and lower power than its predecessors LPDDR4 and LPDDR4x.  Want a copy of the specification?  Click Here Highlighted below are some of the key differences over the previous generation LPDDR4/LPDDR4X: Higher data rate up to 6400MT/s New features for Automotive Applications including: New packaging Optional Link ECC Multi-clocking architecture allows for the Data and the Address/Command/Control to have separate yet synchronous clocks.  This makes capture of the A/C/C much easier and cost effective for development teams. Multi-bank architecture.  LPDDR5 introduces 3 different programmable bank architectures.  The are: BG Mode = 4 banks, 4 bank groups 8B Mode = 8 banks, no bank groups (Like LPDDR4) 16B mode = 16 banks, no bank groups Non Targeted ODT (On Die Termination) for the DQ data signals to support the higher data rate.  This is where the ODT for parts that are not being accessed is driven. The addition of DFE to help deliver an eye at the higher data rates.  Like DDR5 we expect to see this ‘turned on’ at data rates over 4400MT/s. Power Savings features: Dynamic Frequency and Voltage Scaling for the Core and I/O Selectable Differential or Single Ended Clocks and Read Data Strobes Partial Array Self-Refresh and Auto Refresh Two new Commands to help power consumption by reducing data transmission What applications are the target for the new LPDDR5 standard?  The largest is the mobile cell phone and tablet market.  The second largest would be automotive.  The one thing I see missing in the LPDDR5 standard is someway of measuring...

LPDDR5 Detective

  LPDDR5 Detective FEATURES SET-UP TRIGGER & STORE QUALIFICATION PROTOCOL COMPLIANCE PERFORMANCE ANALYSIS TARGET PROBING ORDERING INFO LPDDR5 DETECTIVE FEATURES   Provides logic analyzer like deep transaction Listing and Waveform capture Can store up to 512M of captured States at up to 6400+ MT/s Continuous, real time analysis, not post-processing 2D (voltage & time) Eye Detector guarantees valid data acquisition on each signal Extensive Triggering and Storage Qualification allows precise insight Industry Leading Protocol Violation Detector provides hundreds of simultaneous, real time tests to JEDEC specifications, NOT post processing.  No other tool can provide this! Mode Register Listing provided Supports Auto-Clock rate detect and clock stoppage support Connects to the target under test with Flying Lead, BGA interposers or a midbus probe Integrated Microsoft Charts gives quick insight into large trace captures Trigger In & Out allows the Detective to integrate with other test tools Multi-Bank mode support included LPDDR5 Detective FIltered State Listing LPDDR5 Detective Filtered Waveform LPDDR5 Detective Set-up   Easy Setup Guide steps the user through the process DDR Detective automated setup calibrates to your target and bus speed in minutes. This allows for use in marginal systems Dual Frequency set points are supported automatically Final MRS values are automatically loaded into the protocol analysis tools. LPDDR5 Detective Configuration LPDDR5 Detective Eye Detector LPDDR5 Detective MRS Listing LPDDR5 Detective Triggering and Store Qualification Triggering Features Full control of Trigger Position from 5% – 95% Post store. Adjustable trace depth from 5K to 512M States No need to define 4 states for a Command trigger, the Detective has them pre-defined. External Trigger In and Out Bit specific...

LPDDR4 to LPDDR4X: What is the difference?

Hello Memory Enthusiasts!  Please see here a guest post by the distinguished Patrick Moran  Thanks Pat for allowing the repost! LPDDR4 was introduced in 2014 about two years after LPDDR3. This was probably the fastest transition for a new generation memory ever in JEDEC history. New products and features being introduced into the mobile ecosystem requiring faster and lower power memory propelled the fast development. LPDDR4 succeeded in increasing maximum data rates from 1866 Mbps to 3200 Mbps. But active power results for initial products were disappointing since operating voltage was reduced by only 7%. The industry responded with LPDDR4X early in 2017. The ‘X’ stands for ‘eXtra’ or ‘eXtended’. It headlined lower I/O voltage to save system power and new features to kick the data rate from 3200 to 4266 Mbps. Today it has replaced the original LPDDR4 for new designs (LPDDR4 remains available for legacy systems.) Think of LPDDR4X as LPDDR4 done right. What makes a good LP DRAM and where did LPDDR4 come up short? Two things really – active power and standby power. Maximum active power occurs when the mobile device is operating at full speed, for example playing an action game, and includes memory device power and the power the system uses to operate the memory. An aggressive goal for a new generation of LP DRAM might be the same power at its full speed for the new generation LP DRAM. For example, a LPDDR4 at its max speed of 3200 Mbps might consume the same power as a LPDDR3 operating at its max speed of 1600 Mbps. The least aggressive goal would be that...

What is DDR4 Memory Gear-Down Mode?

A Reliability, Availability and Serviceability  (aka RAS) feature more clearly documented in the new JEDEC DDR4 Rev B spec, Gear-down mode, allows the DRAM Address/Command and Control bus to use every other rising clock of the DDR4 Memory bus clock. The Memory Controller indicates that it wants the DRAM to operate in Gear-down mode by setting bit 3 in Mode Register 3 at boot time.  The system then follows this operation with a sync pulse which is a single clock assertion of Chip Select.  The DRAM then notes that sync pulse assertion and sync’s to that rising clock edge.  It then uses every other rising edge of the clock after that.  So even though the memory controller clock frequency has not changed the DRAM only uses every other edge. Since the data uses both edges of the clock and now the DRAM Address/Command and Control uses every other edge of the rising clock they refer to it as ¼ rate or 2N.  Normally the Address/Command/Control uses only the rising edge of the clock. This is called ½ rate. The screen shot below shows what the bus actually looks like from the memory controller’s point of view in Gear-down mode. Waveform as seen on the FS2800 DDR Detective To reflect what the DRAM is actually using the test equipment needs to be able to adjust to gear-down mode and show what the DRAM is actually seeing on the DDR4 memory bus. State Listing as seen on the FS2800 DDR Detective, what the DRAM sees for DDR4 bus operations while in gear-down mode. Some little nuances come to light when a...
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