Want to Ca$h in on Bitcoin, BlockChain and Cryptocurrency? Speed up your DDR Memory Accesses

Attention all Bit Coin, Ethereum Miners, Block Chain Fans and Distributed Ledger Technology experts.  Do you REALLY understand the computing limits of your hardware?  These applications are among the most compute intensive applications today.  Like most compute intensive applications DDR Memory is involved. There is some confusion over memory bandwidth versus memory latency.  Latency is the time to first access.  See below examples of a memory subsystem running well below the minimum latency allowed by the JEDEC DDR4 specification for some parameters.  Identifying these bottle necks can dramatically increase your memory access time thus your mining application.  Tuning your system for minimum latencies can add $$ to your crypto wallets. Figure 1:  DDR4 Memory Latencies measured on every clock cycle continuously.  Measurement made by the DDR Detective from FuturePlus Systems Bandwidth on the other hand is the amount of data that can be transferred over a certain time.  This is the Mega Bytes per Second metric.  See below.  This metric is important as it determines the amount of data bandwidth that can be sustained over a longer period of time.  If your latency can be improved this number will also improve. Figure 2:  DDR4 Memory Bandwidth measured on every clock cycle continuously on a per bank per rank basis.  Measurement made by the DDR Detective from FuturePlus Systems If your mining hardware is using the latest DDR4 Memory there is another metric (over DDR3) that needs to be considered.  That is Bank Group tuning.  In DDR4, back to back transactions to the same Bank Group, results in a performance penalty.  Back to back accesses to different Bank Groups is...

Fast 3200MT/s DDR4 SODIMMs

FAST SODIMMS for DDR4 are here! Traditionally SODIMMs (Small Outline DIMM) have been used in the mobile environment because of their smaller size.  For DDR3 SODIMMs did not have ECC so they were not even considered for Servers.  When DDR4 was created there was discussions within JEDEC for SODIMMs to be used in more robust environments so ECC was added to the specification.  However, due to the smaller mechanical size of an SODIMM, memory capacity is limited.  Here at FuturePlus we make sure all our DDR Validation Tools work in a variety of systems and at all supported speeds.  The best way to do that is to validate our tools in as many platforms as we can get our hands on.  Which leads me to this little baby! Yes this ASRock is water cooled!  We had some fun setting it up and adjusting the mood lights it comes with to make the water look pretty.  It has 4 SODIMM channels and each channel is a single slot.  In addition these SODIMMs are vertically mounted.  Those of you who are true SODIMM fans know that in most cases the SODIMMs are mounted on an angle so as to reduce vertical height. So how does this memory bus look? ASROCK SODIMM 3200MT/s: Measurement made with a FuturePlus Systems FS2836 and a Keysight Logic Analyzer Take a look at those EYES!  This is a burst scan of both the read data and write data.  You can see that the eyes allow for ample margin for signal capture.  This Asrock system looks, well….rock solid! ASROCK SODIMM 3200MT/s: Measurement made with a FuturePlus Systems...

Is your DDR4 Memory Controller Compliant?

Finally!  After 2 ½ years FuturePlus Systems was successful in sponsoring JEDEC’s first document on protocol checks, JEP175 DDR4 Protocol Checks.  But we didn’t do it alone!  Many thanks to the other Test and Measurement vendors, EDA vendors and Silicon vendors who took the time to review, comment and contribute.  This document was driven by the need to standardize the rules behind a memory controller’s accesses to the DDR4 DRAM.  Absent the Alert signal, which only asserts for Address/Command Parity or CRC errors, the DRAM has no way to tell the Memory Controller ‘hey you just did an incorrect command sequence or you violated command timing’.   The result of incorrect accesses may not be apparent immediately as that location or adjacent locations may not be accessed right away.  The result can be data corruption. The document is the WHAT not the HOW as these measurements can be made with a Logic Analyzer, Mixed Signal Oscilloscope, Protocol Analyzer (think DDR Detective) or implemented as part of a simulation test bench.   The figure below gives a quick overview of how the Protocol Checks are defined in the new JEP175 DDR4 Protocol Checks Document. Figure courtesy of FuturePlus Systems There are dozens of checks defined in the document but they are in no way the definitive list of ALL possible DDR4 Protocol Checks.  We had to start somewhere so this is the list that was agreed upon.  In order to assist in plugging in all the defined values for the various DDR4 B speed bins (1600, 1866, 2133, 2400, 2933 and 3200, MT/s) FuturePlus Systems has gone one step further and created...

Critical Memory Performance Metrics for DDR4 Systems: Page Hit Analysis

Page Hit and Miss is often a metric used to describe caching architectures.  In this context a Hit is when the page was already open and the Read/Write transaction occurred.  A Miss is when an Activate[1] had to occur just prior in order to open the page.  Opening a page takes time and burns power.  An Unused is when the page was opened and then closed with no transaction targeting it.  Memory Controllers use various locality of data algorithms to keep pages open to improve performance.  That is, they open pages ahead of time in order to improve Hit rate.  If they guess wrong and a page was not needed it ends up being closed without being used.  This not only hurts performance because it takes time to open and close pages, but it wastes power as an open page burns more than a closed one.   To gain maximum insight this should be broken down on a per-direction (Read or Write), per-Channel, per-Rank or per-Bank basis.  Below is an example measurement of this metric. [1] Per the JEDEC DDR4 standard an Activate command opens a row (also referred to as a page) and a Precharge command closes it. WHY Measure this? A page is an allocated space in memory that the controller must ‘open’ prior to reading or writing to.  If pages are allocated and never used performance and power is wasted.  Measuring this gives insight into various page allocation algorithms. Software targeting different applications can act very differently with regards to memory page allocation. By understanding this metric different memory architectures and software can be designed for a better...

FS2600 R/LRDIMM

    FS2600 DDR5 RDIMM/LRDIMM Interposer exclusively for use with the Keysight U4164A logic analysis modules The fastest DDR capture tools in the industry…AGAIN! The FS2600 is our newest and fastest logic analyzer probe used to test DDR5 RDIMM and LRDIMM memory. It is designed to work exclusively with 4 Keysight U4164A logic analysis modules operating in either Quad Sample State or Quarter Channel 10GHz timing modes. This gives the user an extremely effective tool for debugging, testing and verifying DDR5 RDIMM/LRDIMMs and DDR5 Memory Channels. Interposer Design – The FS2600 DDR5 DIMM probe does not sacrifice a memory slot, so you can probe any RDIMM/LRDIMM, even in a fully populated memory bus. FS2601 DDR5 UDIMM Interposer pending JEDEC final pinout (Available NOW!) FS2602 DDR5 SODIMM Interposer pending JEDEC final pinout (Available NOW!) FS2605 DDR5 DIMM Satellite Interposer for Slot 2 same channel (Available NOW!) All signals are probed passively. Complete and accurate State analysis. Quarter Channel Timing mode provides deep 10GHz asynchronous sampling of all Data signals. Measure signal integrity of each bit on the DDR5 DIMM with Keysight EyeScan application. View Example Screenshot. Compatible with latest JEDEC RDIMM and LRDIMM pinout. Quick and easy interposer connection between the DDR5 RDIMM/LRDIMM memory bus connector and the U4164A Keysight logic analyzer module. Provides for both CHA and CHB full Data and Address/Command/Control decode. Short DDR5 probe etch length makes it more reliable in marginal systems. Note: FuturePlus has carefully simulated and designed this FS2600 probe to work in your system and it extends the DDR5 bus less than 1.0 inch. Other factors can have a significant effect on the...
Request More Information/Quote or Call: (603) 472-5905
Send
Request More Information/Quote or Call: (603) 472-5905
Send