News, Articles and Updates
DDR5 Clock Stopping and Frequency Change
Having worked on and used the JEDEC DDR specifications for over 20 years we like to look for various improvements that each generation of these specifications bring. One of our favorites is clock stopping. For those of us in the Test and Measurement industry this is...
DDR5 has a new Sideband Bus
Based on the I3C basic specification from the MIPI Alliance, the DDR5 Sideband Bus is official known as JESD 403-1 JEDEC Module Sideband Bus. It is quite the upgrade from the System Management Bus based on I2C that was used for DDR4. The NEW DDR5 Sideband Bus,...
What’s the latest for DDR4 3D Stacked DRAM?
Samsung 256GB DDR4 3DS 2933 RDIMM Well first of all, the JESD 79-4, 3D Stacked DRAM spec has been updated. The new revision is -1B released last month (February 2021) and you can find a copy on the JEDEC web site. The language has been modified to remove offensive...
DDR5 FAQ
These are answers to some of the most frequently asked questions regarding DDR5. When will DDR5 be available to the public? DDR5 will most likely be commercially available in 2022. There are currently three companies that are currently sampling DDR5 DRAMS: SK...
The Threat That Just Keeps Getting Bigger: DRAM Row Hammer
One of the more recent papers from Carnegie Mellon University and ETH Zurich tries to forewarn the tech industry about the prevalence of DRAM Row Hammer failures and lay out possible strategies to combat it. The testing they performed of the DRAM devices (DDR3,...
Who is to blame for DDR Memory ECC errors?
Is it the DIMM or the System? For DDR4 DIMMs and SODIMMs (that support ECC) the ECC (Error Correcting Code) is calculated by the Memory Controller for each byte on a write. A single bit per byte is provided as part of the calculation and is stored in a different...
What do you mean there is NO Validation Report?
In our Services department we see all sorts of systems, network switches, routers, and medical devices, etc. They all share a common theme….the DDR Memory does not work right. The engineers sending us these problem systems are frustrated and we often hear ‘we started...
Row Hammer. The problem no DRAM vendor wants to talk about, except for one, Zentel
Zentel’s new DDR3 DRAM has published data showing zero Row Hammer failures. I fondly recall talking to a large vendor’s ‘tiger team’ concerning Row Hammer failures a few years back. I asked them what should their DDR3 users do if they start to experience Row...
Who won the Logic Analyzer Wars?
We learned recently that Tektronix has discontinued the last of its logic analyzer family. Sigh….Here at FuturePlus Systems we walked the careful balance between the two Whales, Tektronix and HP/Agilent/Keysight. Mostly siding with the later and only crossing over to...
LPDDR5 vs LPDDR4: What’s the difference?
Recently JEDEC announced the new JESD209-5 Low Power Double Data Rate 5 (LPDDR5) specification. LPDDR5 is faster and lower power than its predecessors LPDDR4 and LPDDR4x. Want a copy of the specification? Click Here Highlighted below are some of the key differences...
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