The Threat That Just Keeps Getting Bigger: DRAM Row Hammer

  One of the more recent papers from Carnegie Mellon University and ETH Zurich tries to forewarn the tech industry about the prevalence of DRAM Row Hammer failures and lay out possible strategies to combat it. The testing they performed of the DRAM devices (DDR3, DDR4, and LPDDR4) helped to illustrate the magnitude of this error which appears to get worse for newer technologies. This means that Row Hammer is a problem that needs to be addressed sooner rather than later. Row Hammer is an electrostatic interference glitch that affects nearby cells and causes what is called “bit flips”. A bit flip in turn makes a “zero” into a “one” and vice versa.   This characterization study also explores the organization of the DRAM technology in order to thoroughly explain the Row Hammer error and give suggestions moving forward. The easiest suggestion included refreshing the memory more frequently which increases the charge of the victim row thus making it less susceptible to bit flips. But this suggestion takes a toll on power consumption and performance which is very important to data center operators. The other suggestion is to reconsider the design of DRAM at the component level which DRAM manufacturers are unwilling to do.   This in depth exploration helps readers understand the Row Hammer error a little better. It offers insight into the prevalence of the error in older technologies versus newer technologies. It also offers suggestions on how to mitigate the error. There are big risks with newer technologies having higher vulnerabilities to attacks such as Row Hammer. Hopefully as more research dives deep into this topic,...

Row Hammer. The problem no DRAM vendor wants to talk about, except for one, Zentel

Zentel’s new DDR3 DRAM has published data showing zero Row Hammer failures.  I fondly recall talking to a large vendor’s ‘tiger team’ concerning Row Hammer failures a few years back.  I asked them what should their DDR3 users do if they start to experience Row Hammer failures.  Their response? ‘Upgrade to DDR4!’.  ‘How convenient’ I responded, ‘forcing the industry to throw away all those DDR3 based systems so you can sell more DDR4’.  And come to find out, DDR4 although a bit better, still experienced Row Hammer failures! We here at FuturePlus Systems are glad to see our colleagues in academia are still hunting down those Row Hammer vulnerabilities (https://rambleed.com/).  They can feel good about causing the industry to look for solutions, and it appears that Zentel has answered the call. To the best of our knowledge Zentel has the ONLY Row Hammer hardened DDR3 memory on the market.  See the Zentel data sheets here.  #rowhammer, #DDR3, #JEDEC, #AP Memory,...

Want to Ca$h in on Bitcoin, BlockChain and Cryptocurrency? Speed up your DDR Memory Accesses

Attention all Bit Coin, Ethereum Miners, Block Chain Fans and Distributed Ledger Technology experts.  Do you REALLY understand the computing limits of your hardware?  These applications are among the most compute intensive applications today.  Like most compute intensive applications DDR Memory is involved. There is some confusion over memory bandwidth versus memory latency.  Latency is the time to first access.  See below examples of a memory subsystem running well below the minimum latency allowed by the JEDEC DDR4 specification for some parameters.  Identifying these bottle necks can dramatically increase your memory access time thus your mining application.  Tuning your system for minimum latencies can add $$ to your crypto wallets. Figure 1:  DDR4 Memory Latencies measured on every clock cycle continuously.  Measurement made by the DDR Detective from FuturePlus Systems Bandwidth on the other hand is the amount of data that can be transferred over a certain time.  This is the Mega Bytes per Second metric.  See below.  This metric is important as it determines the amount of data bandwidth that can be sustained over a longer period of time.  If your latency can be improved this number will also improve. Figure 2:  DDR4 Memory Bandwidth measured on every clock cycle continuously on a per bank per rank basis.  Measurement made by the DDR Detective from FuturePlus Systems If your mining hardware is using the latest DDR4 Memory there is another metric (over DDR3) that needs to be considered.  That is Bank Group tuning.  In DDR4, back to back transactions to the same Bank Group, results in a performance penalty.  Back to back accesses to different Bank Groups is...
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