by Barbara Aichinger | Jun 30, 2022 | Uncategorized
Having worked on and used the JEDEC DDR specifications for over 20 years we like to look for various improvements that each generation of these specifications bring. One of our favorites is clock stopping. For those of us in the Test and Measurement industry this is a frequent topic of discussion. State Mode (where we use the bus clock) is the most efficient use of trace memory and the best way to test if the memory bus is doing the right thing. Clock stopping tends to give us a bit of heart burn because if you have no clock all your logic stops. Now, when the clock stops, the bus is not doing anything anyways so you might think this is ok. However, we like to know how long the bus is stopped for. So, to do this we have to employ an alternate clock to help time these events. This might sound pretty straightforward, however, in the past the specifications were not really clear as to when the clock was allowed to stop, for how long, and when it can restart. In addition, many things need to happen before the clock is stopped, like closing all the banks, putting the DRAM into Self Refresh Mode, etc. So, from a test perspective we like to know EXACTLY when the clock will stop (give us a little warning please….) and when it will restart. For DDR4 there was a signal called CKE (Clock Enable). This signal gave a hint as to when the clock was valid. However, it was also used to signal Power Down Entry and Exit while the...
by Barbara Aichinger | Jul 27, 2021 | Uncategorized
Based on the I3C basic specification from the MIPI Alliance, the DDR5 Sideband Bus is official known as JESD 403-1 JEDEC Module Sideband Bus. It is quite the upgrade from the System Management Bus based on I2C that was used for DDR4. The NEW DDR5 Sideband Bus, drawing courtesy of JEDEC . This bus connects all the functions on the DIMMs, RDIMMs, LRDIMMs and SODIMMs in various DDR5 system configurations. Each one of these devices (functions) has its own JEDEC specification. Designers also have to be aware that the bus itself has a specification (and the bus its based on, MIPI I3C, has a specification). In addition the SPD/Hub has two specifications as one is the device and the other is the contents. So counting them all up gives you 8 different specifications that you have to sift through to fully understand what is going on with this new bus. Here is a list of all the specifications: JESD 403-1 JEDEC Module Sideband Bus MIPI I3C Basic specification JESD300-5 SPD5118, SPD5108 Hub and Serial Presence Detect Device Specification JESD400-5 DDR5 Serial Presence Detect Contents JESD301-2 PMIC5100 PMIC (UDIMM, SODIMM) JESD301-1 PMIC50x0 PMIC (RDIMM, LRDIMM, NVDIMM) JESD 302-1 TS5111, TS5110 Serial Bus Thermal Sensor Device Specification JESD82-511 DDR5RCD01 Registering Clock Driver Typical DDR5 RDIMM Sideband Bus devices/functions ,SThe JESD 403-1 is now available for free on the JEDEC website https://www.jedec.org/system/files/docs/JESD403-1-01.pdf The basic architecture of the DDR5 Sideband bus is still a single controller that drives the bus with all the functions acting as responders. Although the MIPI specification allows for multiple controllers, through an arbitration mechanism, the JEDEC Task Group...
by Barbara Aichinger | Mar 3, 2021 | Uncategorized
Samsung 256GB DDR4 3DS 2933 RDIMM Well first of all, the JESD 79-4, 3D Stacked DRAM spec has been updated. The new revision is -1B released last month (February 2021) and you can find a copy on the JEDEC web site. The language has been modified to remove offensive terms, Master has been replaced with Primary. They finally deleted the reference to TRR. This stands for Targeted Row Refresh. Removed from DDR4 (but present in LPDDR4), Targeted Row Refresh was once the answer to Row Hammer failures. Alas no remedy for Row Hammer has yet to be widely implemented. The new updated spec adds more detail as to how many Refreshes can be postponed. For 8Gb and below density die, a maximum of 8 Refresh commands per logical rank can be postponed. For 16Gb and above density die the number of burst refresh commands per 3D stacked PACKAGE is limited to a maximum of 16. Multiple successive Refreshes would cause all of the die in the package to pull on additional current thus causing a potential power drop across the module. The new spec also adds clarity on how many Refreshes can be ‘pulled in’ (done early) and specifies the maximum interval between refreshes for the various heights 2H, 3H or 4H (dies) in a 3DS package. Some optional timing parameters were added concerning Refresh. tRFC is the symbol that defines the parameter REF command to ACT or REF command time to the same logical rank. For 16Gb densities, an optional timing column was added to the Refresh Parameters table that allows for a shorter time between the ACT...
by Lindsay Aichinger | Dec 17, 2020 | DDR5 Memory, LPDDR5, Uncategorized
These are answers to some of the most frequently asked questions regarding DDR5. When will DDR5 be available to the public? DDR5 will most likely be commercially available in 2022. There are currently three companies that are currently sampling DDR5 DRAMS: SK Hynix, Samsung, and Micron. Will we see DDR5 in a laptop? Yes. The new JEDEC spec shows that the DDR5 262 Pin SODIMM has a different mechanical notch that will be different from DDR3 and DDR4. So a DDR5 SODIMM is not capable of being installed in a DDR3 or DDR4 laptop. Will DDR5 require a new motherboard? Yes. This is because DDR5 and DDR4 will not be compatible. New DDR5 Motherboards will most likely be out in 2022. Will mobile phones be available with DDR5? No. DDR5 is for Servers, Desktop and laptops. LPDDR5 will be for mobile phones. Will DDR5 be available for gaming? Perhaps. GDDR5 will be a better alternative. How much will DDR5 cost? DDR5 will be more expensive than DDR4 initially. The cost will depend on supply and demand. Will there be a DDR3 or DDR4 to DDR5 adapter? No. There are too many protocol, power, and ground differences on the pin out. Like DDR3 and DDR4 the notches will be in different places (on DIMMs and SODIMMs) which means you physically cannot plug them in. DDR3: DDR4: ...
by Lindsay Aichinger | Oct 6, 2020 | Data Center, Uncategorized
One of the more recent papers from Carnegie Mellon University and ETH Zurich tries to forewarn the tech industry about the prevalence of DRAM Row Hammer failures and lay out possible strategies to combat it. The testing they performed of the DRAM devices (DDR3, DDR4, and LPDDR4) helped to illustrate the magnitude of this error which appears to get worse for newer technologies. This means that Row Hammer is a problem that needs to be addressed sooner rather than later. Row Hammer is an electrostatic interference glitch that affects nearby cells and causes what is called “bit flips”. A bit flip in turn makes a “zero” into a “one” and vice versa. This characterization study also explores the organization of the DRAM technology in order to thoroughly explain the Row Hammer error and give suggestions moving forward. The easiest suggestion included refreshing the memory more frequently which increases the charge of the victim row thus making it less susceptible to bit flips. But this suggestion takes a toll on power consumption and performance which is very important to data center operators. The other suggestion is to reconsider the design of DRAM at the component level which DRAM manufacturers are unwilling to do. This in depth exploration helps readers understand the Row Hammer error a little better. It offers insight into the prevalence of the error in older technologies versus newer technologies. It also offers suggestions on how to mitigate the error. There are big risks with newer technologies having higher vulnerabilities to attacks such as Row Hammer. Hopefully as more research dives deep into this topic,...
by Barbara Aichinger | Jan 23, 2020 | Data Center, Uncategorized
Zentel’s new DDR3 DRAM has published data showing zero Row Hammer failures. I fondly recall talking to a large vendor’s ‘tiger team’ concerning Row Hammer failures a few years back. I asked them what should their DDR3 users do if they start to experience Row Hammer failures. Their response? ‘Upgrade to DDR4!’. ‘How convenient’ I responded, ‘forcing the industry to throw away all those DDR3 based systems so you can sell more DDR4’. And come to find out, DDR4 although a bit better, still experienced Row Hammer failures! We here at FuturePlus Systems are glad to see our colleagues in academia are still hunting down those Row Hammer vulnerabilities (https://rambleed.com/). They can feel good about causing the industry to look for solutions, and it appears that Zentel has answered the call. To the best of our knowledge Zentel has the ONLY Row Hammer hardened DDR3 memory on the market. See the Zentel data sheets here. #rowhammer, #DDR3, #JEDEC, #AP Memory,...
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