Who won the Logic Analyzer Wars?

We learned recently that Tektronix has discontinued the last of its logic analyzer family. Sigh….Here at FuturePlus Systems we walked the careful balance between the two Whales, Tektronix and HP/Agilent/Keysight. Mostly siding with the later and only crossing over to the ‘dark side’ at the customer’s request. I remember vividly visiting the impressive Beaverton Tektronix campus, hat in hand touting our superior interposers and hardware skills looking for the elusive key to the Tektronix software development environment so we could sell into that market. Once we started down the Tektronix path we had to carefully dodge the wrath of our best friend Agilent. Like the old Girl Scout song I sang as a child “make new friends but keep the old….one is silver and the other gold”. Tektronix was Silver but Agilent was clearly Gold. The wars started in the early 2000’s with one large vendor in particular pitting the two giants against each other. It was brutal with every little technical spec thrown back in our faces as the One Large Vendor led us into the ring to chew each other to death. As it turns out the One Large Vendor had made a costly mistake…..they never thought that if they pushed too hard one vendor would walk. As it turned out one of them did and the remaining Whale charged big and delivered what ever they wanted. The One Large Vendor was able to entice the other Whale back into service a few years later and the wars heated up again around 2010. Then the Logic Analyzer business began a slow and steady decline. The reasons were...

DDR5: The new JEDEC standard for Computer Main Memory

JEDEC’s DDR5 Announcement certainly came as no surprise to those of us working on the standard behind the scenes. The new 5th generation memory bus will have two, 32 bit channels complete with its own Address/Command and Control signals. ECC and CRC will be part of the error checking protocol. This is the first time in the DDR Memory line of standards that will put 2 channels on a single DIMM. Why go to a 32 bit bus? On DDR4 if the slot was in REFRESH, ZQCAL or other ‘stalled’ state the entire RANK was off line to memory traffic. By having a separate channel the Memory Controller can time the maintenance commands to always have some memory available. The increase in burst length to 16 will give the missing bandwidth of going from a 64 bit bus down to a 32 bit bus. The big news on DDR5 is the double data rate nature of the Address/Command and Control bus. In order to keep the DIMM pin count to the 288, which is what we have for DDR4, the number of pins dedicated to the Address/Command/Control needed to be reduced. So the commands are passed on both the rising and falling edges of the clock. The Address is also handled the same way so it can take 4 clock edges, 2 clock cycles, to pass a command and associated address. Although the host bus will be double data rate on the Address/Command/Control the DRAM part itself will be single data rate. The RCD will handle the conversion. There is also an option for single data rate Address/Command/Control and...
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