by Barbara Aichinger | Jun 30, 2022 | Uncategorized
Having worked on and used the JEDEC DDR specifications for over 20 years we like to look for various improvements that each generation of these specifications bring. One of our favorites is clock stopping. For those of us in the Test and Measurement industry this is a frequent topic of discussion. State Mode (where we use the bus clock) is the most efficient use of trace memory and the best way to test if the memory bus is doing the right thing. Clock stopping tends to give us a bit of heart burn because if you have no clock all your logic stops. Now, when the clock stops, the bus is not doing anything anyways so you might think this is ok. However, we like to know how long the bus is stopped for. So, to do this we have to employ an alternate clock to help time these events. This might sound pretty straightforward, however, in the past the specifications were not really clear as to when the clock was allowed to stop, for how long, and when it can restart. In addition, many things need to happen before the clock is stopped, like closing all the banks, putting the DRAM into Self Refresh Mode, etc. So, from a test perspective we like to know EXACTLY when the clock will stop (give us a little warning please….) and when it will restart. For DDR4 there was a signal called CKE (Clock Enable). This signal gave a hint as to when the clock was valid. However, it was also used to signal Power Down Entry and Exit while the...
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