DDR5 has a new Sideband Bus

Based on the I3C basic specification from the MIPI Alliance, the DDR5 Sideband Bus is official known as JESD 403-1 JEDEC Module Sideband Bus.  It is quite the upgrade from the System Management Bus based on I2C that was used for DDR4. The NEW DDR5 Sideband Bus, drawing courtesy of JEDEC . This bus connects all the functions on the DIMMs, RDIMMs, LRDIMMs and SODIMMs in various DDR5 system configurations.  Each one of these devices (functions) has its own JEDEC specification.  Designers also have to be aware that the bus itself has a specification (and the bus its based on, MIPI I3C, has a specification).  In addition the SPD/Hub has two specifications as one is the device and the other is the contents.  So counting them all up gives you 8 different specifications that you have to sift through to fully understand what is going on with this new bus. Here is a list of all the specifications: JESD 403-1 JEDEC Module Sideband Bus MIPI I3C Basic specification JESD300-5 SPD5118, SPD5108 Hub and Serial Presence Detect Device Specification JESD400-5 DDR5 Serial Presence Detect Contents JESD301-2 PMIC5100 PMIC (UDIMM, SODIMM) JESD301-1 PMIC50x0 PMIC (RDIMM, LRDIMM, NVDIMM) JESD 302-1 TS5111, TS5110 Serial Bus Thermal Sensor Device Specification JESD82-511 DDR5RCD01 Registering Clock Driver Typical DDR5 RDIMM Sideband Bus devices/functions ,SThe JESD 403-1 is now available for free on the JEDEC website https://www.jedec.org/system/files/docs/JESD403-1-01.pdf The basic architecture of the DDR5 Sideband bus is still a single controller that drives the bus with all the functions acting as responders.  Although the MIPI specification allows for multiple controllers, through an arbitration mechanism, the JEDEC Task Group...
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