What is DDR4 Memory Gear-Down Mode?

A Reliability, Availability and Serviceability  (aka RAS) feature more clearly documented in the new JEDEC DDR4 Rev B spec, Gear-down mode, allows the DRAM Address/Command and Control bus to use every other rising clock of the DDR4 Memory bus clock. The Memory Controller indicates that it wants the DRAM to operate in Gear-down mode by setting bit 3 in Mode Register 3 at boot time.  The system then follows this operation with a sync pulse which is a single clock assertion of Chip Select.  The DRAM then notes that sync pulse assertion and sync’s to that rising clock edge.  It then uses every other rising edge of the clock after that.  So even though the memory controller clock frequency has not changed the DRAM only uses every other edge. Since the data uses both edges of the clock and now the DRAM Address/Command and Control uses every other edge of the rising clock they refer to it as ¼ rate or 2N.  Normally the Address/Command/Control uses only the rising edge of the clock. This is called ½ rate. The screen shot below shows what the bus actually looks like from the memory controller’s point of view in Gear-down mode. Waveform as seen on the FS2800 DDR Detective To reflect what the DRAM is actually using the test equipment needs to be able to adjust to gear-down mode and show what the DRAM is actually seeing on the DDR4 memory bus. State Listing as seen on the FS2800 DDR Detective, what the DRAM sees for DDR4 bus operations while in gear-down mode. Some little nuances come to light when a...

DDR4 3DS DIMMs: The next big thing in the Data Center

In order to give DDR4 a mid life kicker memory vendors are up’ing their game and producing 3DS DDR4 DIMMs.  What is 3DS you ask?  Its 3 Dimensional Stacking of die in a single package.  Not to be confused by ‘twin die’ which is just 2 die next to each other and not stacked.  3DS uses TSV (through silicon via’s) to make the connection between the dies. 3DS is a game changer when it comes to density.  DIMMS of 128GB, 256GB and possibly 512GB on a single DIMM is enabled by this technology.  RDIMMs or LRDIMMs can implement 3DS and have up to 4 ranks. The 3DS protocol works by introducing the concept of logical ranks in addition to physical ranks. The screen shot below from the DDR Detective shows what the traffic on a 3DS DDR4 memory bus looks like. Waveform showing interleaved traffic between the different physical and logical ranks on a single DDR4 3DS DIMM. The 3DS protocol is also different, as timing parameters between the physical ranks and the logical ranks have to be controlled.  FuturePlus Systems, who took the lead role in JEP 175 DDR4 Protocol Checks, has also created the 3DS protocol checks found in the 3DS option of its FS2800 DDR Detective product. DDR Detective 3DS specific violations.  These run continuously never missing a clock edge and can run for days checking to make sure no potential for data corruption due to protocol errors occur. What’s in your Server?  Well if its 3DS you will want to make sure you’re getting your money’s worth as these DIMMs can be $4000 or more...
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