Speed up your Servers Memory Performance by Understanding Rounding!

Those of you who read my previous Blog post on the new DDR4 Revision B spec know that DDR4 has a much better defined Rounding Algorithm. So why is this important? The Early Days Timing parameters in JEDEC DDR specs are sometimes listed in nanoseconds, microseconds or milliseconds. When testing or simulating logic that runs on the DDR bus one often has to convert time listed in ns, us or ms into clock cycles and a non-integer number results. Since clock cycles occur in integers only we have to either round up or round down. As a carryover from spec to spec over the years there were various notes in the spec that referred to a ‘simple round up’. As the specifications evolved more timing parameters were added to the spec and the notes became sparser and sparser as to how to handle all these new parameters. With the advent of DIMMs and SODIMMs there needed to be a method for having a specific value or an allowable range of values be associated with a particular DIMM or SODIMM and a method to list other optional features that were implemented on that particular DIMM/SODIMM. Thus the SPD was created. SPD stands for Serial Presence Detect. This eprom like part is on every DIMM and SODIMM and is read by the BIOS in order to properly configure the DIMM/SODIMM for the system that it is residing in. So what does the SPD got to do with Rounding? Well the folks that work on that specification quickly realized the issue and the need for a specified rounding method. When the BIOS...

Is your DDR4 Memory Controller Compliant?

Finally!  After 2 ½ years FuturePlus Systems was successful in sponsoring JEDEC’s first document on protocol checks, JEP175 DDR4 Protocol Checks.  But we didn’t do it alone!  Many thanks to the other Test and Measurement vendors, EDA vendors and Silicon vendors who took the time to review, comment and contribute.  This document was driven by the need to standardize the rules behind a memory controller’s accesses to the DDR4 DRAM.  Absent the Alert signal, which only asserts for Address/Command Parity or CRC errors, the DRAM has no way to tell the Memory Controller ‘hey you just did an incorrect command sequence or you violated command timing’.   The result of incorrect accesses may not be apparent immediately as that location or adjacent locations may not be accessed right away.  The result can be data corruption. The document is the WHAT not the HOW as these measurements can be made with a Logic Analyzer, Mixed Signal Oscilloscope, Protocol Analyzer (think DDR Detective) or implemented as part of a simulation test bench.   The figure below gives a quick overview of how the Protocol Checks are defined in the new JEP175 DDR4 Protocol Checks Document. Figure courtesy of FuturePlus Systems There are dozens of checks defined in the document but they are in no way the definitive list of ALL possible DDR4 Protocol Checks.  We had to start somewhere so this is the list that was agreed upon.  In order to assist in plugging in all the defined values for the various DDR4 B speed bins (1600, 1866, 2133, 2400, 2933 and 3200, MT/s) FuturePlus Systems has gone one step further and created...

JEDEC DDR4 Revision B Spec: What’s different?

The JEDEC JC42.3 committees have issued the B version of the DDR4 specification. This version is several years in the making as the original JESD 79-4 DDR4 SDRAM specification was released in September 2012 and the A version published in November of 2013. Those of us in JEDEC have been using the task group version of this spec for several years, finally it is available to non JEDEC members. So what is new and exciting about this B revision? Let’s take a look! Ballouts A X32 ballout was added so we can get a 32 bit bus in a single package. Provisions were also added for a 2 die stack in this configuration. Editorial Updates Several changes to make things clearer. This is in response to ambiguities and misunderstandings that have happened over the years with the A version Single Rank Dual Die per package This specifies how to put 2 x8 die to create a x16 configuration. 8GB,16GB and 32GB addressing was also specified. Targeted Row Refresh Contrary to popular belief TRR is NOT in the final B version. It was for a while, but then removed. Originally, this was in response to the Row Hammer issues of DDR3. Looks like the DRAM vendors found another way to reduce RH failures for DDR4 other than making the Memory Controller babysit frequently accessed Rows. DDR4 does exhibit fewer Row Hammer failures….but it still has some Row Hammer failures (that’s a whole different article!) 3DS Although there is a separate specification for 3DS, the B version does add additional CAS/CW latencies for 3DS. Post Package Repair This is enabled/disabled in...
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