JEDEC’s DDR5 Announcement certainly came as no surprise to those of us working on the standard behind the scenes. The new 5th generation memory bus will have two, 32 bit channels complete with its own Address/Command and Control signals. ECC and CRC will be part of the error checking protocol. This is the first time in the DDR Memory line of standards that will put 2 channels on a single DIMM. Why go to a 32 bit bus? On DDR4 if the slot was in REFRESH, ZQCAL or other ‘stalled’ state the entire RANK was off line to memory traffic. By having a separate channel the Memory Controller can time the maintenance commands to always have some memory available. The increase in burst length to 16 will give the missing bandwidth of going from a 64 bit bus down to a 32 bit bus. The big news on DDR5 is the double data rate nature of the Address/Command and Control bus. In order to keep the DIMM pin count to the 288, which is what we have for DDR4, the number of pins dedicated to the Address/Command/Control needed to be reduced. So the commands are passed on both the rising and falling edges of the clock. The Address is also handled the same way so it can take 4 clock edges, 2 clock cycles, to pass a command and associated address. Although the host bus will be double data rate on the Address/Command/Control the DRAM part itself will be single data rate. The RCD will handle the conversion. There is also an option for single data rate Address/Command/Control and...
Necessary cookies are absolutely essential for the website to function properly. This category only includes cookies that ensures basic functionalities and security features of the website. These cookies do not store any personal information.
Any cookies that may not be particularly necessary for the website to function and is used specifically to collect user personal data via analytics, ads, other embedded contents are termed as non-necessary cookies. It is mandatory to procure user consent prior to running these cookies on this website.