--> May, 2017 | FuturePlus Systems - Part 2

Critical Memory Performance Metrics for DDR4 Systems

Second only to the speed of the processor, memory subsystems design dominates a server’s performance.  The three traditional metrics of Latency, Bandwidth and Power Management are no longer enough to categorize the performance of modern Server memory subsystems.  Memory channels are increasing in speed and the protocol is becoming more complex, the latest being the JEDEC standard DDR4.  As such, new metrics need to be employed to understand and categorize memory subsystem traffic.  By studying the complex, and what is assumed to be random, traffic patterns, we can begin to design and architect the next generation of memory subsystems and servers.  To do this we need to employ some advanced methods of analysis.  The methods employed in the past use a traditional logic analysis approach where only small fractions of a microsecond of memory bus traffic are captured with minutes of dead time between those snapshots trace the cycle by cycle traffic.  The resulting traces are then off loaded and an extensive post processing to glean performance metrics is performed.  This process is expensive due to several reasons: logic analyzers that operate at these speeds are easily in excess of US$150,000 and deep trace depth is expensive and in some cases add an additional US$50,000 to the cost of the analyzer.  After the data has been acquired there is the manpower to write the software that performs the analysis.  In addition, this method is incomplete as the vast majority of traffic is not analyzed due to the inadequate trace depth and dead time between acquisitions.  Thus a new method needed to be derived.  That method is the use of...
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