by Barbara Aichinger | May 2, 2017 | DDR4 Memory
Page Hit and Miss is often a metric used to describe caching architectures. In this context a Hit is when the page was already open and the Read/Write transaction occurred. A Miss is when an Activate[1] had to occur just prior in order to open the page. Opening a page takes time and burns power. An Unused is when the page was opened and then closed with no transaction targeting it. Memory Controllers use various locality of data algorithms to keep pages open to improve performance. That is, they open pages ahead of time in order to improve Hit rate. If they guess wrong and a page was not needed it ends up being closed without being used. This not only hurts performance because it takes time to open and close pages, but it wastes power as an open page burns more than a closed one. To gain maximum insight this should be broken down on a per-direction (Read or Write), per-Channel, per-Rank or per-Bank basis. Below is an example measurement of this metric. [1] Per the JEDEC DDR4 standard an Activate command opens a row (also referred to as a page) and a Precharge command closes it. WHY Measure this? A page is an allocated space in memory that the controller must ‘open’ prior to reading or writing to. If pages are allocated and never used performance and power is wasted. Measuring this gives insight into various page allocation algorithms. Software targeting different applications can act very differently with regards to memory page allocation. By understanding this metric different memory architectures and software can be designed for a better...
by Barbara Aichinger | May 2, 2017 | DDR4 Memory
For DDR4 there are 11 different modes and these metrics are Rank based. These include the following: Reset, Idle, Active, Precharge Power Down, Active Power Down, Maximum Power Down Mode, Self-Refresh, DLL Disable, Write Leveling, MPR Mode (also known as Read leveling or Read training), and VREF Training Mode. To make the best use of this measurement these modes should be represented by the amount of time spent in each mode as Time (in seconds), or percentages (time spent in mode divided by elapsed time). WHY Measure this? Gives engineers a relative measure as to how often various modes are entered and for what length of time the system spends in these overhead states. General Verification of the JEDEC specified modes of operation. To quickly look for infrequent events. A quick analysis of no boot scenarios. To isolate problems in Memory Validation. Power Management is included in this metric so it may seem like a redundant measurement but the new insight gained is in the additional modes and how they all interrelate. Below is an example measurement on our example DDR4 system. The real insight is gained by the second by second playback to show the movement of the system in and out of these various modes. Summary Due to the advancements in FPGA technology, FPGA based test equipment can now count every cycle, transaction and time spent in almost all important events. This allows memory subsystem performance measurements to be expanded to give greater insight into DDR4 performance. Bus Mode Analysis is one of those new metrics that can be tracked on any DDR4 DIMM or SODIMM...
by Barbara Aichinger | May 2, 2017 | DDR4 Memory
If you are Facebook and its 3 am on the East Coast of the United States you probably want to see your Servers in a low power state. This can save you money and make your server farms more ‘green’. For DDR4 there are several ways to help reduce power consumption. They are: PreCharge Power Down Active Power Down Self Refresh Max Power Savings Reducing the frequency and stopping the clock Key metrics here are not only the entering of these states but how long the memory stays in these states. In addition, additional power savings can be had if the clock is stopped during these power saving modes. Measurement and analysis of these events is key to maximum power savings. These metrics should show percentages (used cycles versus total cycles, or versus CKE qualified cycles) and be broken down on a Channel, Slot, and Rank basis. Another key metric would be the amount of seconds or cycles spent in each mode. Why measure this? Cost Savings Memory Controller Code changes to increase power savings can be evaluated and verified Software efficiency: comparing two pieces of code that accomplish the same task functionally may be different with regards to power management. Summary The trade-off between Power Management and Performance is a never ending tug of war. If you want high performance you will pay for it with more power consumption. So some applications may be very aggressive with power management, like Facebook, but others, like high frequency traders want high performance. So burn baby...
by Barbara Aichinger | May 2, 2017 | DDR4 Memory
There are two types of latency to consider when looking at the cycle by cycle transmission of data on the DDR4 Data Bus. The first is the time between the Read or Write command and the data associated with that command, refered to as CAS and CAS Write latency, and then there is the time between successive Read/Write Commands. Latency exists in these two cases in order to give the DRAM time to find, in the case of a READ, and accept in the case of a Write, the data. The time between successive transactions is because the DRAM needs to recover from the previous operation before it can accept a new one. Latency is a key factor in determining Performance. In the next diagram you will see where the important JEDEC separation parameters or protocol checks are measured on a DDR4 bus. Note the orange colored boxes. This is an example of where the system is operating under the specification, in other words leaving some performance on the table. For latency you want to exhibit what we call the ‘Goldilocks’ principle, not too long, not too short but just right. Meaning the memory controller is issuing transactions right at the specification. This ensures that bus is not leaving any performance on the table and critical applications can take advantage of the higher DDR4 speeds. Summary I once had a very experienced engineer from a major server vendor say to me. “ Barb, if you can save us 1 clock tic out of a hundred, that’s a 1% performance improvement and for servers that is a big deal.” By...
by Barbara Aichinger | May 2, 2017 | DDR4 Memory
This is the heart of any Server memory subsystem performance measurement. How much data can be passed within a second. Data bus utilization’s can be expressed as rates (MB per Sec) or as percentages indicating utilization (used cycles divided by total cycles, or CKE qualified cycles) and these can be broken down on a per-direction (Read/Write), per-Channel, per-Rank, or Per-Bank basis. OTF (on the fly) which is a changing from a 4 data beat burst to an 8 data beat burst needs to be handled properly in these calculations. WHY Measure this? Comparing systems memory performance Verify the traffic is what you would expect given the software you are running and if you are running a memory test to see if the system is being stressed. To discern Read performance from Write performance and to help optimize software. To compare various memory controller/DRAM designs to see which one runs faster on an actual hardware level. The below chart shows the MB/s contribution for Reads and Writes for each Bank in the system. If a chip kill or page retirement took place due to memory errors this type of analysis would show the reallocation of memory traffic and the degradation of performance. Summary How many Mbytes/second is an important metric but it only matters if you’re pushing large amounts of memory across the bus at a sustained rate. In reality that rarely happens. Most applications are bursty in nature and don’t require large amounts of information streamed to and from the processor constantly. This is why the next performance metric, Latency, is important. We will talk about that metric in...
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