Specifications - 1680 and 1690 Benchtop Logic Analyzers

Channels 136, 102, 68, 34

State Analysis
State speed 200 MHz
State memory depth Standard: 256K
State memory depth Deep: 1M
Minimum state clock pulse width 1.2ns
Time tag resolution 4ns or +/-0.1%, whichever is greater
Maximum time count between states 17 seconds
State clock/qualifiers 4 (2 on 34 channel models)
Minimum master-to-master clock time 2.5 ns
Minimum master-to-slave clock time 2.0 ns
Minimum slave-to-master clock time 5.0 ns
Setup/hold time (Single clock, single edge) 2.5 ns window adjustable from 4.5/-2 ns to -2.0/4.5 ns in 100 ps increments per channel
Setup/hold time (Multiple clock, multi edge) 3.0 ns window adjustable from 5.0/-2 ns to -1.5/4.5 ns in 100 ps increments per channel

Timing Analysis
Timing speed 400/800 MHz (full/half channel)
Timing memory depth Standard: 512K/1M (full/half channel)
iming memory depth Deep: 2M/4M (full/half channel)
Sample period, full channels 2.5 ns to 1 ms
Sample period, half channels 1.25 ns
Sample period accuracy +/-(0.01% of Sample period +/- 100 ps)
Channel-to-channel skew <1.5ns typical
Time interval accuracy +/-(Sample period accuracy + channel-to-channel skew +0.01% of reading)

Triggering
Sequencer speed >200 MHz
Maximum occurrence counter 16,777,215
Range width 32 bits
Timer value range 100 ns to 5497 seconds
Timer resolution 5 ns
Timer accuracy 10 ns +/-0.01% of setting
Trigger resources 16 patterns, 15 ranges
Timers 3 (136 channels), 2 (102 channels), 1 (68 channels),
0 (34 channels)
Occurrence counters 1 per sequence level
Trigger sequence levels 16
Trigger in arms logic analyzer 15 ns typical delay
Trigger to Trigger out 150 ns typical delay

Probes
Input resistance 100 K Ohms +/- 2%
Parasitic tip capacitance 1.5 pf
Maximum input voltage +/- 40V peak
Minimum voltage swing 500 mV p-p
Threshold range -6V to + 6V in 10 mV increments
Threshold accuracy +/-(65mV + 1.5% of setting)