Characteristics - FS4415 SRIO Protocol Preprocessor
For use with Tektronix Logic Analyzers

• Data acquisition in 8b Decoded Data mode at 3.125, 2.5 or 1.25 Gbps (reference clock recommended)
• Reference clock frequencies:
  • 1.25 Gbps is supported with an external reference clock of 62.5 MHz  (x20 ref)
  • 2.5 Gbps is supported with an external ref clock of 125 MHz (x20 ref) or 100 MHz (x25 ref as done in PCIe)
  • 3.125 G is supported with an external ref clock of 156.25 MHz (x20 ref)
• Lane modes: x1 lane and x4 lane (able to select x1 probing on lane 0 or lane 2).
• Lane deskew (align) in x4 lane mode.
• Supports debug of physical, transport and logical layers (messaging, I/O and streaming
• Detects, displays, filters in/out, and allows triggering on the following events in 8b Decoded Data Mode:
  • Silence
  • Invalid serial byte (code violation or disparity error detected, but not displayed)
  • Idle Sequence
  • Control Symbols with Stype0 and Stype1
  • Control Symbols within packets
  • Packet Types 0 through 15
  • Packet Spreading of x1 link data to 4 column format

  FS4416 is available to add PCI Express analysis capability. Switching between the two is accomplished via the Probe Manager Software.

  Power Requirement - +5V DC (external supply included)

  USB connector for probe control from a PC