Features - FS4410
Serial Rapid IO Protocol Analysis Probe For use with Agilent Logic Analyzers
Low cost Serial Rapid IO protocol analysis
X1 and X4 lane widths supported
Performs lane alignment (lane deskew)
Detects packet types and checks packet delimiters (minimal protocol checking)
User can enable or disable de-scrambling
Provides packet-aware Data Filtering (Store Qualification) and Logic Analyzer triggering
Provides 3 24-byte packet header recognizers (on any combination of bits)
Supports up to two machines for upstream and downstream directions or for two unrelated single direction links
User can select lane inversion and lane numbering reversal as needed to probe the board under test
User can set probe into 10 bit mode (external reference clock required) to view 8b/10b encoded data to debug phy level and link initialization problems. Lane deskew, 8b/10b error checking are included. Packet delimiters are visible in the listing.
Probe Manager software executing on a PC controls probe over a USB interface in real time
Both 40-pin and 90-pin logic analyzer connectors included, no termination adapters required
Probe powered from external supply, not your system
Probe event log records link status: lane number, time and quantity of receiver errors
