Features - FS4405
PCI Express Protocol Preprocessor For use with Tektronix Logic Analyzers
Monitors two directions of X1, X2, X4 and X8 links
Performs lane alignment (lane deskew) for PCI-Express
Detects packet types and checks packet delimiters (minimal protocol checking)
Provides means for user to enable or disable de-scrambling
Provides packet-aware Data Filtering (Store Qualification) and Logic Analyzer triggering
Provides three 24-byte packet header recognizers (on any combination of bits)
Supports upstream and downstream directions
or for two unrelated single direction links on a single TLA module.
User can select lane inversion and lane numbering reversal as needed to probe the board under test
User can set probe into 10 bit mode (external reference clock required) to view 8b/10b encoded data to debug phy level and link initialization problems. Lane deskew, 8b/10b error checking are included. Packet delimiters are visible in the listing.
Probe Manager software executing on a PC controls probe over a USB interface in real time
Probe powered from external supply, not your system
Probe event log records link status: lane number, time and quantity of receiver errors
