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Specifications - FS4200 IEEE 1394 Analysis Probe Screen Captures The FS4200 IEEE-1394 Bus Analyzer is a IEEE-1394 node with three ports. It participates in the bus initialization, tree identification and self-identification processes required of a 1394 node. It is compliant with the IEEE 1394-1995 and IEEE 1394-A specifications. The FS4200 provides an electrical and mechanical interface from Agilent logic analyzers to the IEEE-1394 serial bus. The software included with the FS4200 contains complete configuration files and a 1394 Protocol Decoder for your Agilent logic analyzer. Simply attach your Agilent logic analyzer pods, load the appropriate logic analyzer configuration file and you are ready to begin analysis. The FS4200 gives the user a powerful tool in the debugging, testing and verifying of IEEE 1394 designs. In State Analysis mode, the analyzer master clock is derived from the PHY-Link interface clock to generate a header clock and a data phase clock. (Note this allows a user to capture only header information if memory depth is a problem). Packet information, either header information or data, is clocked up a quadlet (32 bits) per analyzer clock. The analyzer is clocked only when a packet or an event has been detected on the PHY-Link interface, thus optimizing memory utilization. In Timing Analysis mode, the PHY-Link interface may be viewed directly without any interpretation. This will allow a designer to see exactly what is being presented on the PHY-Link interface. The IEEE-1394 analyzer probe also provides four 50 ohm SMA connectors that are connected directly to the signal pairs TPA/TPA* and TPB/TPB* on one of the three ports. These connectors may be used to connect an oscilloscope to the analysis probe for direct observation of the serial bus signals. Agilent 16900 Protocol Decode
Agilent 16900 Protocol Decode
Timing Analysis
Analog Analysis
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Copyright 2006 FuturePlus Systems Corporation |
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