Features
- FS4100 Universal Serial Bus (USB) Analysis Probe
Passive USB bus analysis
Complete USB serial to parallel decode
Automatic detection and operation at high-speed (12Mbits/s) or
low-speed (1.5Mbits/s), including dynamic speed changing
Automatic USB reset detection
Address and end point specified in token packet held until transfer
completes
Allows for easy triggering, store qualification and performance
monitoring of specific end points
Timing Analysis Mode allows analysis of the actual serial bit stream
Supports the full USB specification
Supports all types of data transfers, including isochronous transfers
Supports dynamic hot swapping
Use your existing Agilent logic analyzer! Requires only 2 pods!
Complete configuration files and USB Transaction Inverse Assembler
supplied for your Agilent logic analyzer
Uses Agilent's enhanced triggering capabilities, cross-domain analysis,
store qualifiers, and system performance software for complete USB
performance monitoring
Accurate time-stamping for both State and Timing Analysis modes
FuturePlus Systems has recently introduced important new measurement
capabilities in the USB Bus Analysis Probe, FS4100. These changes are
denoted by version code "F". Users who have purchased an FS4100 with
a prior release code may contact
FuturePlus Systems to order an upgrade kit for their unit. The charge
for this upgrade kit is $300 (10% higher outside of USA or Canada), FOB
New Hampshire, USA. The upgrade is user installable (requires replacing
a ROM). Order "FS1005 USB Firmware Upgrade to Version F".
An error summary status is implemented in this design. If the Analysis
Probe detects any one of the following errors: CRC error, serial
bit stuffed error, bad pid, invalid pid, then the error summary status
will be reported by the analyzer.
Once a Reset is detected, a status of USB RESET is clocked to the
analyzer. At the end of the Reset, a status of RESET END is clocked
to the analyzer. This allows the user to see the occurrence and duration
of Resets without using excessive analyzer memory.
RESUME signaling is terminated with an SE0, followed by a J STATE
signaling sequence. These states are reported as a separate status
to the analyzer so the user can check durations and specification
compliance.
In the previous design, a single CRC status was used for DAT0 and
DATA1 packets. The current release uses DATA0 CRC and DATA1 CRC.
This allows protocol checking for Control transfers.
If a SOF is sent at Slow speed, a new status is clocked to the
analyzer.
If the Analysis Probe detects a signaling sequence involving an
SE0 of two samples (sample duration dependent on the current operating
speed of the bus) it will look for the appropriate J STATE. If the
incorrect J STATE is seen then the Analysis Probe sends a status
POSSIBLE BAD EOP. Note: in a quiescent line (IDLE) if extraneous
SE0 (not glitches but signaling long enough for two samples to be
detected) occurs then this status will be sent.
Chapter 9 decode of the USB specification has been added to the
Inverse Assembler (shipping since REV 1.1 of the software).
Additional symbols have been added to the configuration files to
reflect the above additions.
KEEP ALIVE detection was implemented to the specification of the
sender. This was too rigorous, resulting in the FS4100 not reporting
all KEEP ALIVE events. KEEP ALIVE status was reported at the end
of a USB RESET. Both of these problems are fixed.
A more robust method of latching the result of the CRC checking
logic at the appropriate time has been implemented.
The serial bit stuffed error latch was not implemented optimally.
This characteristic may cause the FS4100 to fail to report a Serial
Stuffed bit error. The new implementation latches the serial stuffed
bit error for the duration of the packet.
The Suspend status was being reported after 1 ms of Idle time on
the bus instead of 3 ms; this is fixed.
The Suspend status was being reported after 1 ms of Idle time on
the bus instead of 3 ms; this is fixed.
The shift inhibit generated from a stuffed bit caused the FS4100
to not latch the correct status on packets that have a value of 3F
in the low byte of the CRC data. This is fixed.
