FS3100 System Requirements

Untitled Document

System Requirements - FS3100 32- or 64-bit VME/VXI Analysis Probe

Agilent 1680-, 1690 and 16900-series Logic Analyzers

Bus Configuration	Pods Required for Protocol Analysis	Pods Required for Protocol and Timing Analysis
32 bit address, 32 bit data	5	6
32 bit address, 64 bit data	7	8
64 bit address, 64 bit data	9	10

For timing analysis of BR0-BR3, BBSY, BCLR, IRQ1-IRQ6, BERR/IRQ7, IACKIN, IACKOUT and DTACK, an additional pod is required.
Double-probing Y connectors are provided for configurations that require more than 6 pods.
The FS3100 does not require Termination Adapters.
A logic analyzer pod has 17 channels.
We recommend you use the latest Agilent operating software to insure you will get the best performance from FuturePlus products. To get the latest 1670/16700 logic analyzer software click here.

16900/902/903 Modules	Description	Pods Available
16740-741-742A	200 MHz State/400 MHz Timing, 2 GHz Timing Zoom	4
16750-751-752A	400 MHz State/400 MHz Timing, 2 GHz Timing Zoom	4
16910A	250 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom	6
16910A in turbo mode	450 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom	lose one pod per machine
16911A	250 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom	4
16911A in turbo mode	450 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom	lose one pod per machine

16800 series Analyzers

16800 series Analyzers	Description	Pods Available
16803A	250 Mb/s State/1 GHz Timing, 4 GHz Timing Zoom	6
16803A turbo	500 Mb/s State/1 GHz Timing, 4 GHz Timing Zoom	lose one pod per machine
16804A	250 Mb/s State/1 GHz Timing, 4 GHz Timing Zoom	8
16804A turbo	500 Mb/s State/1 GHz Timing, 4 GHz Timing Zoom	lose one pod per machine
16806A	250 Mb/s State/1 GHz Timing, 4 GHz Timing Zoom	12
16806A turbo	500 Mb/s State/1 GHz Timing, 4 GHz Timing Zoom	lose one pod per machine

FS3100 VME/VXI
Analysis Probe

No Demo Available