Accurate Protocol and Timing Analysis
The FS2351 DDR3 1066 DIMM memory bus analysis probe brings bus signals to your Agilent logic analyzer via controlled impedance cables for an easy protocol and timing analysis connection while maintaining signal fidelity. The included transactor software translates the signals into easily understood bus transactions at the full bus speed. Extensive triggering and store qualification features are available through the Agilent logic analyzer. All signals are probed passively before being sent to the logic analyzer. Burst sizes of 2, 4, 8, are supported.

The user can elect to view either write cycles, read cycles, or combination write-and-read cycles.

DIMMs supported

The FS2351 supports a 240-pin, 533 MHz clock (1066 MT/s data rate), 64-bit, Unbuffered Synchronous Double Date Rate (DDR) DRAM Dual In-Line Memory Module (DDR SDRAM DIMM). It also supports slower versions down to 100 MHz (200 MT/s data rate). Registered and non-registered DIMM's are supported.

Note: Electrically, the FS2351 extends the DDR3 bus approximately 1.0 inch in etch length. Depending on the design of the system being tested, users may experience difficulties with this extension of the DDR3 bus. There are two logic analyzer termination loads on each Data signal and just one on the Command, Control, and Address signals. These passive logic analyzer terminations are low capacitance, high impedance terminators and provide a matched impedance to the logic analyzer. The analysis probe includes cables for seven logic analyzer modules. Factors beyond the control of FuturePlus Systems that can have a significant effect on the performance of the whole DDR3 system include the type of memory controller, the target layout, the type of DIMM used, which DIMM socket is being probed, and which logic analyzer cards are being used.