FS2105 Features

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Features - FS2105 PCI-X 133 MHz, 64-bit Active Analysis Probe

Key Features

32 or 64 bit PCI-X bus analysis
0 to 133 MHz operation
Logic Analyzer Configuration Software gets you up and running fast
Complete cycle type identification
De-multiplexed command
12 cycle and transaction identifiers allow for easy triggering on various PCI-X conditions
PCI-X bus protocol decode software designed for easy software and hardware debug
Built-in compliance violation triggering
Agilent's System Performance Analyzer allows key PCI-X performance metrics to be viewed in chart or histogram mode

TECHNICAL DETAILS

FuturePlus Systems and Agilent Technologies have combined their talents to produce a 133 MHz PCI-X state analysis probe for use with Agilent logic analyzers. This product performs complete state analysis of the PCI-X bus and detects over 50 PCI-X compliance violations. The product provides many bus observer signals that allow for easy triggering and store qualification. The bus observer signal group includes such groupings as xact_cmd, bus_state, and term. The "xact_cmd" is the latched command information and is valid from the address phase until the end of the cycle. "Bus_state" indicates what state the bus is in, on every clock tick. These signals allow the user to capture and filter specific bus states.

BUS STATE	MEANING
No_sync	After Reset this state is entered.
idle	Bus is idle both Frame# and IRDY# are deasserted
dac1	The first half of a dual address cycle
addressing	Address phase of a single address cycle
dac2	The second half of a dual address cycle
attribute	This phase provides more information about the cycle
target respond	Where the target claims the transaction by asserting DEVSEL#
wait	TRDY# has not been asserted as yet
transfer	Data transfer is taking place, both IRDY# and TRDY are asserted
recovering	One clock where FRAME# and IRDY# are still asserted and while TRDY# and DEVSEL# are both deasserted.
decoding	One or more clocks between attribute and target respond
termination	One clock after terminations i.e. target abort

Another powerful bus observer signal group is "term"; these signals indicate the following termination conditions: master abort, split response, target abort, single data phase disconnect, retry, disconnect on next ADB, master completion. The protocol compliance checking covers 53 possible violations. An LED display indicates the first violations to occur, and this display is cleared when the protocol checker is reset.

The state listing indicates on four separate states the first violations that have occurred during this capture. The next four states indicate all protocol errors that have occurred during the present run. Each of the 53 possible errors may be masked individually by setting the appropriate masking switch. The FS2105 incorporates the Agilent E2929C exerciser/protocol checker card and thus takes only one PCI-X slot. This solution comes complete with software that runs on the Agilent logic analyzer.

The FS2105 analysis probe requires the use of an Agilent logic analysis system and associated logic analyzer cards. The advantages of this approach to the user are:

Cross correlation of the PCI-X bus data with data monitored elsewhere in the system (cross domain analysis)
A common user interface with previous products. A 66 MHz PCI user will transition easily into the user interface of the FS2105.
Because of the extensive and flexible store qualification and triggering features of the Agilent logic analyzers, the user has the tools they need to solve those problems that are hard to characterize any other way

The PCI-X Bus Active Analysis Probe Adapter provides two functions:

Provides an electrical and mechanical interface from the PCI-X bus to Agilent logic analyzers for active PCI-X bus state analysis.

The PCI-X protocol decode software executes in the Agilent logic analyzer. In State Analysis mode, the analyzer master clock is derived from the PCI-X clock and generated by protocol-sensitive logic. The bus protocol decode software decodes the key PCI-X bus signals and presents a readable display that lists the transaction type, address, data and key status conditions such as wait states and retries. The software also supports user-defined symbols that can be easily added to the state listing display. The PCI-X cycle, transaction identifiers, and demultiplexing of command and address lines make triggering easy and accurate.

All PCI-X cycles and transaction identifiers are decoded by protocol-sensitive clocking logic and represented by bits presented to the logic analyzer.

In the Agilent logic analyzer system, a menu preference allows the user to display bus transactions in terms of common PC accesses such as "video memory" or "RTC/CMOS RAM Data Port". Post processing filters also allow the user to suppress or display various types of transactions.

A stand alone "bus watcher" that detects protocol violations and latches an LED on to indicate a failure has occurred. An external logic analyzer can then be connected to further troubleshoot the error.

Connection to the Agilent Logic Analyzer
The FS2105 connects to the Agilent Logic Analyzer using Termination Adapters. You will need three of them for normal PCI-X protocol analysis. If you also wish to observe protocol violations, you will need an additional Termination Adapter.

Compliance Violation Detection
The FS2105 checks over 50 PCI-X Protocol rules in real-time. Each rule can be individually masked to suppress the triggering of known problems. The rules being checked are derived from the PCI-X Compliance Checklist and the PCI-X Specification, and are designed to find any possible violations of the PCI-X protocol. They are sent as individual signals to the logic analyzer on POD's 7 and 8. An ANYERROR LED on the E2929C indicates the presence of any error. The compliance violations detected are listed below.

PROTOCOL RULE CHECKED	SPECIFICATION REFERENCE
An initiator can terminate a transaction with master abort (de-assert FRAME# and IRDY#) 8 clocks after the address phase(s).	PCI-X Spec 2.11.1.2.
If the target inserts wait states on burst write or Split Completion, the initiator must toggle between its first and second data values until the target asserts TRDY# (or terminates the transaction).	PCI-X Spec 1.10.2. Rule 5
The initiator is required to terminate the transaction when the byte count is satisfied.	PCI-X Spec 1.10.2. Rule 6
The initiator is permitted to disconnect a burst transaction (before the byte count is satisfied) only on an ADB.	PCI-X Spec 1.10.2. Rule 7
Burst Write and Split Completion transactions must not be terminated with Split Response. All other target terminations are permitted.	PCI-X Spec 2.6.1.
The target is permitted to signal Single Data Phase Disconnect only on the first data phase (with or without preceding Wait States).	PCI-X Spec 1.10.3. Rule 6
The target is permitted to signal Split Response only on the first data phase (with or without preceding Wait States).	PCI-X Spec 2.11.2.4.
Once the target has signaled Disconnect on Next ADB, it must continue to do so (or signal Target Abort) until the end of the transaction.	PCI-X Spec 2.11.2.2.
The target de-asserts DEVSEL#, STOP# and TRDY# one clock after the last data phase (if they are not already de-asserted) and floats them one clock after that.	PCI-X Spec 1.10.3. Rule 8
There must be an even number of target initial wait states for a burst write and Split Completion.	PCI-X Spec 2.9.
If a PCI-X target signals Data Transfer (with or without preceding Wait States), the target is limited to disconnecting the transaction only on an ADB (until the byte count is satisfied).	PCI-X Spec 1.10.3. Rule 5
FRAME# cannot be de-asserted unless IRDY# was asserted	PCI Spec Appendix C, Rule 8c
When FRAME# has been de-asserted, it cannot be reasserted during the same transaction.	PCI spec Appendix C Rules 8b and 8d
IRDY# must be asserted two clocks after the attribute phase.	PCI-X Spec 1.10.2. Rule 3b
Initiator Wait States are not permitted	PCI-X Spec 1.10.2. Rule 3b
A transaction starts when FRAME# is asserted for the first time. IRDY# must not go low when FRAME# is high.	PCI Spec Appendix C, Rule 7 and 8c
Once asserted IRDY# must stay asserted until the end of transaction or till the target signals a termination.	PCI-X Spec 1.10.2. Rule 3b and PCI-X Spec 2.9.
TRDY# must not be asserted before the attribute phase, but two or more clocks later.	PCI-X Spec 2.8. Table 2-6 and PCI Spec Appendix C Rule 14
Once TRDY# has been asserted, it must not be de-asserted and reasserted during the same transaction (no subsequent wait states).	PCI-X Spec 1.10.3. Rule 4
DEVSEL# must be asserted prior to the edge at which the target asserts TRDY#.	PCI-X Spec 2.8. and PCI-X Spec 2.9.1.
DEVSEL# must not be asserted during a special cycle or if a reserved command has been used.	PCI-X Spec 2.4. and PCI-X Spec 2.7.3.
DEVSEL# must not be asserted 1, 5 or more than 6 clocks after the address phase.	PCI-X Spec 2.8.
After a Target asserts DEVSEL#, it cannot be de-asserted until the last data phase has completed, except to signal Data Transfer, Wait States, Target Abort, Split Response, Retry and Single Data Phase Disconnect.	PCI-X Spec 1.10.3 Rule 3
DEVSEL# must be de-asserted one clock after last transfer.	PCI-X Spec 1.10.3 Rule 8
STOP# must not be asserted without DEVSEL# being asserted, except RST# being asserted.	PCI-X Spec 1.10.1.Rule 12; PCI spec Appendix C, Rule 14, spec 6
If the target signals Split Response, Target-Abort or Retry, the target must do so within eight clocks of the assertion of FRAME#.	PCI-X Spec 1.10.3 Rule 4
If the target signals Single Data Phase Disconnect, Data Transfer or Disconnect on Next ADB, the target must do so within 16 clocks of the assertion of FRAME#.	PCI-X Spec 1.10.3 Rule 4
ACK64# may only be asserted, when REQ64# was asserted before (ACK64# is a response to REQ64#).	PCI Spec 3.8.
A 64-bit initiator asserts REQ64# with the same timing as FRAME# to request a 64-bit data transfer. It de-asserts REQ64# with FRAME# at the end of the transaction.	PCI-X Spec 2.12.3. Requirement 4
If a 64-bit target is addressed by a transaction that does have REQ64# asserted with FRAME#, the target asserts ACK64# with DEVSEL# to complete the transaction as a 64-bit target. It de-asserts ACK64# with DEVSEL# at the end of the transaction.	PCI-X Spec 2.12.3.
REQ64# must not be used with special cycle or interrupt acknowledge command. Only burst transactions (memory commands other than Memory read DWORD) use 64-bit data transfers.	PCI-X Spec 2.4. and 2.7.
For DWORD Transactions, REQ64# must be de-asserted.	PCI-X Spec 2.12.3. Requirement 2
PERR# may never be asserted three clocks after the address phase (or earlier in a transaction) or during a special cycle. During WRITE, PERR# may be asserted three clocks after IRDY#, during READ, PERR# may be asserted three clocks after TRDY#.	PCI Spec 3.8.2
AD[31::0] address parity error	PCI Spec Appendix C, Rule 32 b
AD[63::32] address parity error	PCI Spec Appendix C, Rule 32 c
AD[31::0] data parity error occurred but was not signaled.	PCI-X Spec 5.3.
AD[63::32] data parity error occurred but was not signaled.	PCI-X Spec 5.3.
AD[31::0] data parity error occurred	PCI Spec Appendix C, Rule 32 b
AD[63::32] data parity error occurred.	PCI Spec Appendix C, Rule 32 c
WARNINGT!!!! In the address phase AD[1:0] must be 0 for DWORD Transactions. spec draft 2.1.1 Reserved commands are reserved for future use.	PCI-X Spec 2.4
DAC is not allowed immediately after a DAC.	PCI Spec 3.9. and PCI-X Spec 2.12.1.
During the data phases C/BE# bus must be driven high for all Burst Transactions except Memory Write.	PCI-X Spec 2.6.
During a Dual Address Cycle, a 64-bit master has to drive the upper half of the address on AD[63::32] in the initial and in the second address phase.	PCI-X Spec 2.12.1.3 a i)
In the second address phase of a Dual Address Cycle, AD [63:32] and AD [31:0] contain duplicate copies of the upper half of the address.	PCI-X Spec 2.12.1.3 a i)
During a Dual Address Cycle, a 64-bit master has to drive the bus command on C/BE [7::4]# in the initial and the second address phase.	PCI-X Spec 2.12.1.3 a ii)
In the second address phase of a Dual Address Cycle, C/BE [7::4]# and C/BE [3::0]# contain duplicate copies of the transaction command.	PCI-X Spec 2.12.1.3 a ii)
DWORD Transactions only support a single data phase.	PCI-X Spec 2.7.
A master that supports 64-bit addressing must generate a SAC instead of a DAC, when the upper 32 bits of the address are zero.	PCI spec 3.9

Cross-Domain Analysis

Are you analyzing data from multiple buses? Simply use this analysis probe to monitor the PCI-X bus, and then use another FuturePlus Systems analysis probe to monitor your other bus. We have analysis probes for the ISA, PMC, USB, VME, VXI, DDR, SIMM and several other buses. You can create your own custom measurement system, cross-domain trigger between buses, and view data from multiple buses simultaneously in the same display.

PCI-X Exerciser

The FS2105 has an optional on-board 64 bit PCI-X exerciser. The exerciser operates at 0 to 133.4 MHz, and can emulate and force practically any behavior of a PCI-X device imaginable, except blatant protocol violations. The exerciser includes a graphical user interface and a command line interface, both supported in a Windows environment. The feature is customer installable as a single card license and is provided by Agilent Technologies as product number E2929C #300. Full pre-sales assistance and post-sales technical support is provided only by Agilent Technologies.

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