Specifications - FS2102 & FS2103 PCI Bus 66 MHz, 64-bit Active Analysis Probe And Extender Card

• 3.3v (FS2102) or 5.0v (FS2103) operation
• 32- or 64-bit PCI bus monitoring
• Up to 66 Mhz operation
• Demultiplexed address and command
• 12 cycle and transaction identifiers allow for easy triggering on various PCI conditions (Click to see list)
• Full 32-bit address counter increments the address to the logic analyzer during burst operations
• Triggers on 21 PCI Specification compliance-violations. (Click to see list)
• Short card form factor and simple logic analyzer connection allows easy in-system debug.
• Agilent's System Performance Analyzer allows key PCI performance metrics to be viewed in chart or histogram mode.

PCI Cycle and Transaction Identifiers
The following cycle identifiers are created by the FS2102 and FS2103 and routed to the logic analyzer:

• Address Valid
• Data Valid
• Retry
• End of Transaction
• Target Abort
• Master Abort
• Wait-initiated by the Target
• Wait-initiated by the Master
• Wait-due to no DEVSEL
• Idle
• Transaction type (latched command)
• Latched Grant

Compliance Violation Detection
These violations are derived from the PCI Compliance Checklist and the PCI Specification. They are sent as individual signals to the logic analyzer on POD's 9 and 10. If any of these errors occur, the signal ANYERROR on POD 2 will assert and will be clocked to the logic analyzer by the master clock. The error signals, the encoded error summary and the signal ANYERROR will be asserted for no more than 2 PCI clock tics. There are additional signals from the Violation CPLD that are available to be used for additional compliance violations. They are currently reserved for future use. The compliance violations detected are listed below.

• ERROR 0 FRAME must be deasserted as soon as possible after STOP is asserted
• ERROR 1 Fast back to back only after WRITE or MASTER ABORT
• ERROR 2 IRDY asserted in the address phase
• ERROR 3 FRAME cannot be deasserted unless IRDY is asserted
• ERROR 4 IRDY must be deasserted after last transfer or when FRAME is deasserted
• ERROR 5 IRDY must not go low when FRAME is high
• ERROR 6 IRDY cannot deassert untill DATA PHASE complete
• ERROR 7 No DEVSEl on reserved or special cycle
• ERROR 8 Once DEVSEL has been asserted it cannot be deassserted until DATA PHASE
• ERROR 9 DEVSEL must be deaserted after the last release
• ERROR10 DEVSEL must be asserted with or prior to TRDY
• ERROR 11 No TRDY in the turn around phase
• ERROR 12 Once TRDY asserts cannot change until DATA PHASE
• ERROR 13 DEVSEL must be asserted with or prior to STOP
• ERROR 14 STOP must remain asserted until FRAME is deasserted
• ERROR 15 TRDY valid in COMMAND CYCLE
• ERROR 16 TRDY valid in a IDLE CYCLE
• ERROR 17 DEVSEL asserted in COMMAND CYCLE
• ERROR 18 FRAME not aserted on CYCLE following DAC
• ERROR 19 STOP asserted during IDLE CYCLE
• ERROR 20 PERR must never be asserted two clocks after ADDRESS PHASE or SPECIAL CYCLE