Features
- FS1141 DDR1 Protocol and Performance
Checking
Tool
The FS1141 checks for the following DDR1 protocol violations:
Refresh with active banks
Write to a bank that is not active
Read from a bank that is not active
Mode register set with active banks
Bank not precharged before being activated
A Data Burst was interrupted by a command
Detailed explanation of the Protocol Violation Analysis Feature
The Functional and Performance Analysis window
allows the user to initiate the analysis of a trace file in either on
or off-line mode using the “Start Analysis” button.
Additionally, when used in on-line mode it can capture a trace file using
the “run” command
or initiate repetitive runs and additive Tool analysis of each run.
In the Statistics section, the performance analysis
of the DDR1 DIMM bus over the entire captured trace file is displayed. This
shows information regarding the total number of clock cycles and commands that
are included in the analyzed trace file, as well as the total number of errors
found. The error count is based on the errors selected in the setup. This
display also includes information on the Read, Write and Data activity
occurring during the captured trace file.
In
the Errors section, the tool displays comprehensive
information about the location and nature of each selected error found in the
captured trace file. The user can scroll through the error listing and either
select one error by left clicking on the error to set a “DDR” marker
in the State and Waveform listings, or the user can select the “Place
Markers on All” button which will place uniquely numbered markers (DDRx)
on all identified errors. Please note: The errors listing is limited to a maximum
of 1,000 errors. Placing markers on all with a large number of errors in the
listing can take several minutes to complete. The error markers allow the users
to switch between the Tool, State, and Waveform information easily during the
analysis of the activity related to an error.
View a Protocol Violations screen sample.
The FS1141 provides the following bus performance statistics
and timing analysis. These measurements provide some indication of the performance
of your DDR1 system during the trace capture:
Bus utilization - percent of write and
read commands
Percent of clock cycles with data activity
Data valid measurements across all channels with multiple data bursts
Detailed explanation of the Bus Performance and Timing Analysis feature: The Timing
Analysis window provides an analysis of each Data
bit’s window during every data burst across an entire Timing
Zoom trace. The user can set a threshold criteria in this window
and then select whether the data windows to be identified should
be equal to, greater than or equal to, or less than or equal to that
value. All Data bits during any burst captured in a TZ trace will
be listed in the Timing Analysis window.
Additionally, the tool provides some overall statistics on what was measured
in the TZ trace that was analyzed. This includes the number of Read and Write
strobes analyzed, the % of data strobes with data transitions occurring; as
well as, the maximum, minimum and average Data Bit widths across ALL bits during
ALL bursts in the TZ trace.
View a Bus
Performance and Timing Analysis screen sample.
Exporting FS1141 Data
Data from either the protocol or timing
analysis screens can be easily exported to a .csv file
This makes it easy for further analysis,
graphing, etc.
The FS1141 requires one of the following Agilent
products
