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System Requirements - DDR2 Embedded Bus Analysis Software

  1. See the table below for logic analyzer requirements for protocol decode.
  2. The FS1124 requires Termination Adapters
  3. A logic analyzer pod has 17 channels
  4. Alternate logic analyzer module configurations for this product
  5. Click Here for information on 16700 series logic analyzers
  6. Click Here for information on Off Line Analysis support for this product
  7. We recommend you use the latest Agilent operating software to insure you will get the best performance from FuturePlus products. To get the latest 1680/1690/16900 logic analyzer software click here.
DDR Bus Speed
Analyzer Type
Timing Analysis
Protocol Analysis

400 MT/s

16750,16751,16752

2 cards configured as one module with one timing machine

4 cards configured as 1 module

 

400 MT/s

 

16910, 16911

2 cards configured as one module with one timing machine

3 cards configured as 1 module

667 MT/s

16950

2 cards configured as one module with one timing machine

4 cards configured as 1 module


16900-series Modules
Description
Pods Available
16750-751-752A 200 MHz State/400 MHz Timing, 2 GHz Timing Zoom 4
16750-751-752A turbo 400 MHz State/400 MHz Timing, 2 GHz Timing Zoom lose one pod per machine
16753-756A 300 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom 4
16753-756A turbo mode 600 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom lose one pod per machine
16753-756A dual sample 800 Mb/s State/1.2 GHz Timing, 4 GHz Timing Zoom 2
16910A 250 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom 6
16910A in turbo mode 450 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom lose one pod per machine
16911A 250 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom 4
16911A in turbo mode 450 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom lose one pod per machine
16950A
300 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom 4
16950A in turbo mode
600 MHz State/1.2 GHz Timing, 4 GHz Timing Zoom lose one pod per machine
16950A dual sample
800 Mb/s State/1.2 GHz Timing, 4 GHz Timing Zoom 2

 



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