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Untitled Document
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System Requirements
- DDR1 Embedded Bus Analysis
Software
Agilent 16700-series Logic Analyzers
- See the table below for logic analyzer requirements for protocol
decode.
- The FS1107 requires Termination Adapters
- A logic analyzer pod has 17 channels
- Click
Here for information on Off Line Analysis support for this product
- We recommend you use the latest Agilent operating
software to insure you will get the best performance from FuturePlus
products. To get the latest 1670/16700 logic analyzer software go
to Agilent's
web site.
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DDR Bus Speed
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Analyzer Type
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Timing Analysis
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Protocol Analysis
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200 MHz
(PC1600)
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16717,16718,16719
16740,16741,16742
16750,16751,16752
16753,16754,16755, 16756
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Two cards configured as one module with one
timing machine
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Four cards configured as 1 module
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400 MT/s
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2 cards configured as one module with one timing
machine
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4 cards configured as 1 module
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16700/702 Modules
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Description
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Pods Available
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| 16717-718-719A |
167 MHz State/333 MHz Timing, 2 GHz Timing Zoom |
4 |
| 16717-718-719A turbo |
333 MHz State/333 MHz Timing, 2 GHz Timing Zoom |
lose one pod per machine |
| 16740-741-742A |
200 MHz State/400 MHz Timing, 2 GHz Timing Zoom |
4 |
| 16750-751-752A |
200 MHz State/400 MHz Timing, 2 GHz Timing Zoom |
4 |
| 16750-751-752A turbo |
400 MHz State/400 MHz Timing, 2 GHz Timing Zoom |
lose one pod per machine |
| 16753-756A |
300 MHz State/1.2 GHz Timing, 4 GHz Timing
Zoom |
4 |
| 16753-756A turbo mode |
600 MHz State/1.2 GHz Timing, 4 GHz Timing
Zoom |
lose one pod per machine |
| 16753-756A dual sample |
800 Mb/s State/1.2 GHz Timing, 4 GHz
Timing Zoom |
2 |
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DDR1 Embedded Bus
Analysis Software
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Copyright 2006 FuturePlus Systems Corporation |
