|
Name
|
Rule
|
Description
|
| Illegal control signal asserted during IDLE |
1
|
Section 3.2.1 Basic Transfer Control |
| PERR# asserted without a parity error |
2
|
Section 3.7.4.1 Data Parity Error signaling on PERR# |
| PERR# not asserted for parity error |
3
|
Appendix C Rule 37c |
| Parity error |
4
|
Appendix C Rule 37b and c |
| Illegal control signal asserted during Address Phase |
5
|
Section 3.2.1 Basic Transfer Control |
| Reserved Command |
6
|
Section 3.1.1 Command Definition |
| AD[1:0] !=00 for Mem Write and Memory Write Invalidate |
7
|
The FS1105 checks for linear incrementing. Section 3.2.2.2 Memory
Space Decoding
|
| Mem Write and Invalidate not started on cacheline boundary |
8
|
The FS1105 checks for cache aligned accesses per the input given
by the user. Section 3.2.2.2 Memory Space Decoding |
| REQ64# asserted in non-memory space command |
9
|
Section 3.10 64 bit bus extensions |
| AD[63:32]=0 in DAC command when REQ64# asserted |
10
|
Section 3.10.1 64 bit Addressing on PCI |
| Delayed transaction (Clocks = xxxxxxxx) not completed within
2**15 clocks |
11
|
Agilent Rule to detect potential deadlocks |
| Delayed transaction (Clocks = xxxxxxxx) not retried within 2**14
clocks |
12
|
Agilent Rule to detect potential deadlocks |
| Illegal control signal asserted 2nd address phase of DAC |
13
|
3.9 64 bit addressing on PCI |
| Reserved or DAC command in the 2nd address phase of a DAC |
14
|
3.9 64 bit addressing on PCI |
| FRAME# de-asserted illegally |
15
|
FRAME# cannot be deasserted unless IRDY# is asserted. Appendix
C rule 8c |
| REQ64# asserted in non-memory space command |
16
|
Section 3.9 64-bit Bus Extensions |
| Inconsistent address in 64-bit transfer |
17
|
"Inconsistent address" means that AD[63:32] does not equal AD[31:0]
in the first address phase. 3.9 64 bit addressing on PCI |
| High address must be non-zero |
18
|
In a DAC the upper address must be non zero. 3.9 64-bit addressing
on PCI |
| Illegal control signal while waiting for DEVSEL# |
19
|
Appendix C Rule 14 and 29 |
DEVSEL asserted after 5 clocks from FRAME# |
20
|
Section 3.3.3.1 Master Initiated Termination |
| FRAME# and IRDY# deasserted before 5 clocks and no DEVSEL# |
21
|
Section 3.3.3.1 Master Initiated Termination |
| Transfer latency > 8 clocks |
22
|
Appendix C Rule 27 |
| IRDY# latency > 8 clocks |
23
|
Appendix C Rule 27 |
| TRDY# initial latency > 16 clocks |
24
|
Appendix C Rule 25 |
| TRDY# subsequent latency > 8 clocks |
25
|
Appendix C Rule 26
|
| DEVSEL# asserted during a special cycle |
26
|
Section 3.7.2 Special Cycle |
