DDR Memory FAQs
DDR Product Overview
DDR1 333 DIMM
DDR1 333 SODIMM
DDR1 400 DIMM
DDR1 Embedded
DDR2 667 DIMM
DDR2 667 SODIMM
DDR2 800 DIMM
DDR2 Embedded
DDR3 1067 DIMM

Q. Which DIMMs does the FS2351 DDR3 Analysis Probe support?

A.  The FS2351 supports a 240-pin, 667 MHz clock (1333 MT/s data rate), 64-bit, Unbuffered Synchronous Double Date Rate (DDR) DRAM Dual In-Line Memory Module (DDR SDRAM DIMM).

Q. Why does the FS2351 require seven logic analyzer cards?

A. The FS2351 requires seven logic analyzer cards for protocol analysis or three logic analyzer cards for timing analysis. The FS2351 requires that the 16950B card be in 1067 Mb/s mode, which allows only 2 pods per card for use. The first card is for ADDR/Cmd signals, cards 2-4 are for WRITE Data, and cards 5-7 are used for READ data. Since the 16900 and 16902 have six slots, this system requires two logic analysis frames. We recommend using 16900 operating system version 3.50 or higher with the FS2351. You may also use the 16753-756 cards. All seven must be the same model number. UPDATE - With the new 16962A card, you only need four for 1333 MT/s analysis.

Q. When do I need to use the new 16950B card with the FS2351? What's the difference from the 16950A/B? Can I use them together?

A. The 16950B has a supported state clock speed of 667 MHz in turbo mode, higher than the 600 MHz of the 16950A. The 16950B also has a smaller minimum data valid window requirement, 550 vs. 600 pS. Lastly, the 16950B has a state data rate speed of 1067 Mb/s, higher than the 16950A's 800 Mb/s. These 16950B features are required by the DDR3 bus running at 1067 MT/s. The 16950A and 16950B can NOT be melded together, the SW will not allow the merger. The 16950A can be melded with 16753/54/55/56A modules.  When melded, the set takes on the lowest memory depth of the modules in the set. The 16951B is the new deep memory (256M) module.  The 16950B and 16951B can NOT be melded.  

Q. Can you guarantee the FS2351 will operate correctly in my system?

A. Another good question. Electrically, the DDR3 bus is extended approximately 1.0 inch in etch length in the design of the FS2351. Depending on the design of the system being tested, users may experience difficulties with this extension of the DDR3 bus. The passive logic analyzer termination presents a single electrical load on the DDR bus via low capacitance, high impedance terminators, and also provides a matched impedance to the logic analyzer. The analysis probe includes seven cables that connect to the logic analyzer modules. Factors beyond the control of FuturePlus Systems that can have a significant effect on the performance of the whole DDR3 system include the type of memory controller, the target layout, the type of DIMM used, which DIMM socket is being probed, and which logic analyzer cards are being used. So, we cannot guarantee your success. We have made every effort to give you a product that has every chance of succeeding.

Q. Can the FS2351 perform Eye Scan measurements?

A. Yes. The FS2351 can do Eye Scan for Command activity clocked by CK0, Chip Select qualification may be required. If the target can generate just Read or Write activity, then a data strobe signal (DQS2, DQS7, or DQS17) can be used to clock Eye Scan for the data signals.

Q. Does the FS2351 DDR Protocol Decoder display ECC?

A. The ECC bits are available on Header 14. However, viewing them may require an additional logic analysis module and modification of existing configuration files.

Q. What software is included with the FS2351 DDR3 Analysis Probe?

A. Files are included that automatically set up the Agilent logic analyzer for state or timing analysis mode and label all the signal names. Another file contains the protocol decoder, which translates the data into memory protocol during state analysis. The DDR Protocol Checker and Performance Analysis software provides measurements of the data window eye width on a bit by bit basis across all Timing Zoom data in the trace file; additionally it identifies those signals with the smallest eye width.

Q. Does the FS2351 include the Transaction Viewer software?

A. No. The FS2351 requires two 16900 or 16902 frames. The Transaction Viewer software has only been designed for one frame at this time.

Q. Does your probe get its power from my system?

A. No. The FS2351 does not have any active circuitry.

Q. When I use my FS2351 in my target, it doesn't boot. Is this a known problem?

A. Possibly. JEDEC changed the function of pin #119 from ground to SA2 after the FS2351 was designed. If your target is using pin #119 as SA2, this will cause a boot problem when the FS2351 is installed. This is simple fix, please contact the factory for instructions on returning it and we will be happy to fix it.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

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