DDR Memory FAQs
DDR Product Overview
DDR1 333 DIMM
DDR1 333 SODIMM
DDR1 400 DIMM
DDR1 Embedded
DDR2 667 DIMM
DDR2 667 SODIMM
DDR2 800 DIMM
DDR2 Embedded
DDR3 1067 DIMM

This page provides answers on some of the more common questions we receive regarding our DDR1 Embedded Analysis solutions.

Q. Which DIMMs does your FS1107 DDR1 Analysis software support?

A. The FS1107 supports registered and non-registered DIMMS. Both x4 and x8 SDRAMS are supported.

Q. How does the Agilent logic analyzer connect to my DDR1 memory system?

A. There are two ways for you to connect the logic analyzer. The first is to design in a special test connector. You can use a Mictor, a Samtec or an Agilent Softouch. Termination Adapters are used to plug into the test connectors. The other end of the termination adapter connects to the logic analyzer pods. The necessary impedance matching networks are included in the termination adapter. The second method uses a chip probe adapter. The chip probe adapters are available from JM Engineering, (719) 591-1119. The chip probe adapter fits down on top of the DDR chip and includes a test lead pin array that you use to connect the logic analyzer "flying lead" adapter. The flying lead adapter connects to the logic analyzer pod. Again, the necessary impedance matching networks are included in the flying lead adapter.

Q. Do you have a product that connects directly to a DIMM socket?

A. Yes. Please see the DDR Overview, linked on the left menu of this page.

Q. What software is included with the FS1107 DDR1 Analysis software?

A. Files are included that automatically set up your Agilent logic analyzer for state or timing analysis mode and label all the signal names. Another file is the protocol decoder, which translates the signals into bus transactions during state analysis.

Q. Is there any power drawn from my system?

A. No.

Q. Which sample clock is used as a reference clock? Is the sample clock computed or is there any physical pin on the DDR slot for us to take as the sample clock? Are they dataclk and commandclk? If the dataclk and commandclk (CK0 and #CK0) are not sent to the non-memory slot by chipset, could we do the inverse assembly and find the correct sample point by eye finder? How do we acquire the exact dataclk and commandclk? Also, if we need to get a DIMM Select, in P.19 of FS1107 manual, where are the three test points, CH13, CH14, CH15? How do we solder the pin onto our pod?

A. The clock used for state capture of DDR data (DQ0-DQ71) is a modified version of DQS0. The DDR probe User's Guide explains the processing done on DQS0 to create the analysis clock. Essentially, the DQS0 strobe is received with a Schmitt trigger to eliminate false clocking (due to reflections on the DDR bus). The timing is then adjusted so that it is delayed by a minimal amount for writes and a larger amount for reads. This processing requires that the probe be able to recognize the commands being sent to the DIMM so that it can compute whether a given burst is a read or a write.

The clock used for state mode sampling of the DDR address/command bus is CK0 and #CK0. If the DDR controller does not drive these signals to DIMM slots that do not identify themselves as DDR memory then the analyzer will not be able to do state data capture on the address/command data or properly compute the analysis clock for state acquisition of DDR write and read data.  If the controller turns off the CK0/#CK0 signals to the DIMM slot containing the DDR Probe, then you have two options for capture of DDR data:

1) Override the controller programming or bring the CK0/#CK0 clocks to the probed DIMM slot from another slot. This will allow full functionality of the probe (i.e. acquisition of read AND write bursts in a single trace)

2) Set the Probe configuration switches (read and write switches should be in the off position) to pass the DQS0 clock directly to the analyzer. EyeFinder can then be used to calibrate the analyzer for capture of either read OR write bursts, but not both. To switch from one burst type to the other, the analyzer must be recalibrated using EyeFinder. This also places constraints on the stimulus used while EyeFinder is run. Specifically, during calibration for reads the stimulus must ONLY do read bursts, and vice versa for writes. This mode assumes that DQS0 is available to all DIMMS (even ones with no memory loaded). Inverse assembly is used only for state mode data. This means that CK0/#CK0 must be active for inverse assembly. Timing mode will work whether the state clocks are available or not.

The DIMM select test points are located on the top part of the board and are labeled "CH15", "CH14", "CH13" to reflect the analyzer channels they are associated with. You should just solder wires directly into the thru hole for the test point you want to use. Each test point has a ground test point next to it so you can use twisted pair wires to improve signal integrity. The other end of the wire can be soldered to the appropriate DIMM select signal on the motherboard or on the appropriate DIMMS.

Q. Can I use the 16760A logic analyzer module with the FS1107 software?

A. At a minimum you will probably need 5 cards ( using time tags), depending on how fast your bus is going. Let's assume 266 MT/s. With 5 cards you will not be able to capture simultaneous reads/writes, simply because you would not have enough pods. If your system is runing at 266, the analyzer will need to run in 400 Mb/s mode which needs a pod pair for time tags ( that is why it goes to 5 cards). If you are only doing timing analysis you will need 4 cards. This setup also assumes 64 bit data bus. We recommend the 16753A - 16756A cards instead.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

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