Q. What software is included with the FS4400 PCI Express Analysis Probe?
A. Files are included that automatically set up the Agilent logic analyzer for protocol decode mode and label all the signal names. Another file contains the protocol decoder, which translates the data into memory protocol during state analysis. This software is compatible with the new Transaction Viewer software, which gives a higher level view of bus transactions. Also included is the Probe Manager software, which runs on a Windows PC and allows the user to remotely control the analysis probe functions.
Q. What cable adapters does the FS4400 include to connect to my target system?
A. Because there are several different ways that customers may need to connect to their system, we do not include any cable adapters with the FS4400. You must choose at least one cable adapter with your FS4400 order. Click here to see the various cable adapters available.
Q. What is the difference between the FS1038 X8 cable adapter and the FS1039 X8 cable adapter?
A. It depends on how you want to rout the signals and which approach may be easier for you. The FS1038 has the lanes for the 2 directions interleaved (each direction in it's own column) and the FS1039 has the lanes from the 2 directions separated (each direction has it's own set of rows).
Q. Why does the FS4400 support the 1680 only in X1 mode?
A. In X1 the PCIe state clock is 200 MHz, within the spec of the 1680. At X4 and above the state clock is 250 MHz, outside the 1680 spec.
Q. Do I need termination adapters to connect the FS4400 to my logic analyzer?
A. No. The FS4400 includes the necessary termination circuitry and connectors for both 40-pin and 90-pin style logic analyzer cables.
Q. Does your probe get its power from my system?
A. No. All necessary power is supplied by an external supply, which is included with the FS4400.
Q. Does your protocol decoder identify disparity errors?
A.Each symbol is tagged as valid or invalid, which means it had either incorrect disparity or was a bad decode.
Q. Will it display the 10b symbols instead of 8b?
A. Yes. The user can set the FS4400 probe into 10 bit mode (external reference clock required) to view 8b/10b encoded data to debug phy level and link initialization problems. Lane deskew and 8b/10b error checking are included. Packet delimiters are visible in the listing.
Q. Do you identify when a link is in compliance mode? This is useful information when a link is not training.
A. Yes, we detect the compliance pattern.
Q. How long does it take for you to get frame lock after a link comes out of electrical idle? If it takes too long, the analyzer will miss symbols after the FTS ordered sets.
A. On a single lane link that repeatedly cycles between operational for 5 uS and in L0s for 24 uS, we acheived N_FTS = 2 (actually under 2). This was using a reference clock connection. Our projections for a 4 lane link operating in spread spectrum, that goes into L0s for the max allowed time on a target with max allowed ref clock jitter are that N_FTS = under 12.
Q. It looks like you are relying on the triggering capability of the analyzer; how do you keep the analyzer from capturing when the link is idle?
A. Actually the FS4400 Probe Manager includes significant Pattern Recognizer features. The Pattern Recognizer can then trigger the logic analyzer. The user may also filter out all IDLE states, then they are never clocked into the analyzer.
Q. When I am just looking at transactions, I like to eliminate skip ordered sets and flow control. To eliminate skip ordered sets you need to know where the comma symbol is going to land. If you do not help this a lot of analyzer resources will be eaten up trying to cover all possibilities. Flow control DLLPs are 8 eight bit symbols long and you have to know where the SDP symbol is.
A. The FS4400 has comprehensive filtering (store qualify) abilities; 58 different kinds of activity may be filtered in or out. Filtering by Virtual Channel and by Traffic class is included. See the FS4400 Probe Manager.
Q. I like to trigger on TLPs. Do you offer assistance with this? The issues I mentioned for Skip ordered sets and flow control are compounded because TLPs are 3 and 4 Dwords long.
A. There are two ways the FS4400 helps with triggering: (1) The start states of every DLLP and TLP are flagged with an event code which may be used for triggerring. (2) A Packet recognizer can be set to flag every TLP in general, or particular kinds of more specific TLPs (or DLLPs).
Q. What happens if FTS does not complete correctly?
A.The FS4400 depends on FTS to acheive lock. Until then, FS4400 N_FTS is not yet specified. If the transmitter doesn't complete FTS, the user might not see any intelligible data displayed. "Link alive" might be indicated if some valid characters are received. If the link then goes to electrical idle, "link down" and/or "electrical idle" may be indicated. The FS4400 will depend on a SKIP Ordered Set following FTS to perform lane deskew. Until the next SKIP occurs, lanes will be unaligned (in a x2 or x4 case).
Q. What do the LED's on the FS4400 signify?
A. These are Quad-state LEDs. Green indicates the link is OK. Orange indicates invalid or unaligned data. Red indicates a receiver fault. Dark indicates a loss of signal.
Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?
A. Contact your nearest Agilent Call Center.
Q. How do I know which Agilent logic analyzer is best for my needs?
A. Click here.
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