The PCI Extended Input Output (EIO) Analysis Probe provides two functions:
The FS3030 provides an electrical and mechanical interface to Agilent logic analyzers for passive PCI EIO bus State Analysis. In State Analysis mode, the analyzer master clock is the PCI EIO clock. The PCI EIO bus disassembler software executes in the Agilent logic analyzer, decoding the key PCI EIO bus signals and presenting a readable display that lists the transaction type, address, data and key status conditions such as wait states and retries.
The software also supports user-defined symbols that can be easily added to the state listing display. The user can also select post-processing filters which allow the acquired data to display only chosen transactions. To assist with triggering, pre-defined resource terms have been included that can be used to prevent WAIT and IDLE states from being acquired, thus saving trace memory and providing an easier-to-read state display. FuturePlus Systems also provides a PCI bus triggering application note to all its PCI Analysis Probe customers.
The FS3030 provides an electrical and mechanical interface to Agilent logic analyzers for passive PCI EIO bus Timing Analysis. In Timing Analysis mode, the analyzer generates the master clock and allows the user to make accurate signal timing measurements.