The software derived module reduction solution cannot qualify more than 3 of the following signals - CKE0, CKE1, CS0, CS1, CS2 and CS3 - at any one time.  This means that data from more than two ranks of a DIMM or SODIMM cannot be viewed simultaneously.  Even for a two rank DIMM or SO-DIMM there are problems if each rank has a unique clock qualification signal, which is often the case.  In that scenario only data from a single rank can be correctly acquired.  Quad rank DIMMs are especially problematic for a software derived module reduction product.  This is because only one rank of data can reliably be acquired at any one time.  In addition a complicated set of choices to swap in and out the above listed qualification signals will need to be selected by the user.  In order to prevent undetectable data corruption during the protocol decode in the logic analyzer state listing screen, the user again needs to intervene and make another complicated selection.  These limitations are not present in a hardware derived solution such as the one from FuturePlus Systems.  The hardware derived solution uses high speed logic to qualify the DDR3 bus and sends a single signal to the TLA7BB4 module.  Thus the logic analyzer resources are preserved and no limitations are present.