Bus Contention and Catastrophic Errors
The data on the DDR bus is only present on the signal lines for a short period of time. The DDR data bus is shared amongst the different DIMMs in a channel and DRAM parts on a DIMM. It is imperative that once read or write data is on the bus, the next read or write data wait until the bus is clear before the new data is put on those same signal lines. This is like a traffic intersection. Don’t enter the intersection if there are already cars in that intersection because if the light turns you might experience a collision! A collision of data on the DDR data bus leads to corruption. Some of this corruption is detectable and correctable but some is catastrophic and will result in a system crash or worse yet undetectable data corruption. The JEDEC specification is detailed in its timing requirements to prevent data collision on the DDR data bus. Even so, we quickly found this violation on this brand new motherboard.