Q. Which DIMMs does your FS2332 DDR2 Analysis Probe support?
A.The FS2332 supports the PC3200 module, a 240-pin, 200 MHz clock (400 MT/s data rate), 64-bit, Unbuffered Synchronous Double Date Rate (DDR) DRAM Dual In-Line Memory Module (DDR SDRAM DIMM). It also supports slower versions that use a 100 MHz (200 MT/s data rate) or a 133 MHz clock (266 MT/s data rate) DDR SDRAM DIMM. Registered and non-registered DIMMs are supported.
Q. Why does the FS2332 take four logic analyzer cards when it only requires four termination adapters?
A. The FS2332 requires up to four logic analyzer cards depending on whether protocol analysis (double probed) or timing analysis is being used, and the type of logic analyzer card being used. A fifth card may be required if all *DQS and SPD-EEPROM signals must be observed simultaneously. The customer will need 4 cards/8 pod pairs/16 pods and 4 - E5378A or 4 - FS1026 termination adapters:
* 2 cards/4 pod pairs/8 pods are needed for the data and command bus
* 1 card/2 pod pairs consumed by the new internal double probing system (multiplexing) for data bus only
* 1 card/ 1 pod pair consumed by Turbo Mode for the data bus
This totals 4 cards/7 pod pairs/14 pods used by this configuration
There is an optional 5th card + 1 termination adapter (using 1 pod pair for signals + 2nd pod pair for internal double probing system
PLEASE NOTE: using the FS2332 may require a 16700 operating system update. Please contact FuturePlus for details.
Q.What are RDIMM's and UDIMM's?
A. UDIMM is an unregistered DIMM and RDIMM is a Registered DIMM. With registered DIMM's the Address/Command information go through buffers. Registered DIMM's are usually used in servers; this allows the user to put more DIMMs on a motherboard than unregistered DIMMs, because the Address/command info go through buffers. The buffers add a delay of 1 clock cycle between when the command is issued to when the data is valid for a read or write. This delay can be compensated through the preferences. The FS2332 supports both UDIMM's and RDIMM's
Q. Why can't I use a 16750-753 class of logic analyzer module with the FS2332? The 16750-753 modules are spec'ed at 400 MT/s which is what the DDR2 bus operates at.
Good question. The FS2332 is supported at up to 667 MT/s with the 16753-756 because of the data valid requirements of the DDR2 bus. The DDR2 bus data valid window can be as low as 900 ps. The 16750-752 cards require a minimum of 1200 ps. The 16753-756 can operate as low as 800 ps. If your data valid window on your bus is higher than 1200 ps you may be able to use the 16750-752 cards. In this case you need to use the E5385A termination adapters, which may pose a mechanical interference problem. The FS1026 termination adapter was designed to work with the 16753-756 cards and makes a 90 degree bend at the probe, thus resolving the potential mechanical interference problem.
Q. Can I use a 16760 logic analyzer module with the FS2332?
At this time we don't include an config file for it, but it would work. The 16760 has 2 pods per card. You will need to use 5 cards, because you need to attach 8 pods to the probe and then you will need 2 pods for turbo mode. If you plan to do this, contact technical support and they will make a config file for you.
Q. Can you guarantee the FS2332 will operate correctly in my system?
A. Another good question. Electrically, the DDR2 bus is extended approximately 1.0 inch in etch length in the design of the FS2332. Depending on the design of the system being tested, users may experience difficulties with this extension of the DDR2 bus. The passive logic analyzer termination presents a single electrical load on the DDR bus via low capacitance, high impedance terminators, and also provides a matched impedance to the logic analyzer. The analysis probe includes four logic analyzer connectors. Factors beyond the control of FuturePlus Systems that can have a significant effect on the performance of the whole DDR2 system include the type of memory controller, the target layout, the type of DIMM used, which DIMM socket is being probed, and which logic analyzer cards are being used. So, we cannot guarantee your success. We have made every effort to give you a product that has every chance of succeeding.
Q. Can the FS2332 perform Eye Scan measurements?
A. The FS2332 can do Eye Scan for Command activity clocked by CK0. If the target can generate just Read or Write activity, then a data strobe signal (DQS2, DQS7, or DQS17) can be used to clock EyeScan for the data signals.
Q. Does the FS2332 DDR Protocol Decoder display ECC? If so, what information is displayed?
A. Yes. The FS2332 Protocol Decoder displays the ECC bits along with the data. After the data is displayed we output CB=XX where XX is the value of the ECC bits in hex.
Q. What software is included with the FS2332 DDR2 Analysis Probe?
A. Files are included that automatically set up the Agilent logic analyzer for state or timing analysis mode and label all the signal names. Another file contains the protocol decode, which translates the data into memory protocol during state analysis.
Q. Does your probe get its power from my system?
A. No. All necessary power is supplied by the logic analyzer.
Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?
A. Contact your nearest Agilent Call Center.
Q. How do I know which Agilent logic analyzer is best for my needs?
A. Click here.
Have a question you don't see answered? Contact Technical Support for a prompt answer.