DDR1 Embedded Analysis Software

This page provides answers on some of the more common questions we receive regarding our DDR1 Embedded Analysis solutions.

Q. Which DIMMs does your FS1107 DDR1 Analysis software support?

A. The FS1107 supports registered and non-registered DIMMS. Both x4 and x8 SDRAMS are supported.

Q. How does the Agilent logic analyzer connect to my DDR1 memory system?

A. There are two ways for you to connect the logic analyzer. The first is to design in a special test connector. You can use a Mictor, a Samtec or an Agilent Softouch. Termination Adapters are used to plug into the test connectors. The other end of the termination adapter connects to the logic analyzer pods. The necessary impedance matching networks are included in the termination adapter. The second method uses a chip probe adapter. The chip probe adapters are available from Delta Design Engineering Corporation, (719) 550-0020. The chip probe adapter fits down on top of the DDR chip and includes a test lead pin array that you use to connect the logic analyzer "flying lead" adapter. The flying lead adapter connects to the logic analyzer pod. Again, the necessary impedance matching networks are included in the flying lead adapter.

Q. Do you have a product that connects directly to a DIMM socket?

A. Yes. Please see the DDR Overview, linked on the left menu of this page.

Q. What software is included with the FS1107 DDR1 Analysis software?

A. Files are included that automatically set up your Agilent logic analyzer for state or timing analysis mode and label all the signal names. Another file is the protocol decoder, which translates the signals into bus transactions during state analysis.

Q. Is there any power drawn from my system?

A. No.

Q. Which sample clock is used as a reference clock? Is the sample clock computed or is there any physical pin on the DDR slot for us to take as the sample clock? Are they dataclk and commandclk? If the dataclk and commandclk (CK0 and #CK0) are not sent to the non-memory slot by chipset, could we do the inverse assembly and find the correct sample point by eye finder? How do we acquire the exact dataclk and commandclk? Also, if we need to get a DIMM Select, in P.19 of FS1107 manual, where are the three test points, CH13, CH14, CH15? How do we solder the pin onto our pod?

A. The clock used for state capture of DDR data (DQ0-DQ71) is a modified version of DQS0. The DDR probe User's Guide explains the processing done on DQS0 to create the analysis clock. Essentially, the DQS0 strobe is received with a Schmitt trigger to eliminate false clocking (due to reflections on the DDR bus). The timing is then adjusted so that it is delayed by a minimal amount for writes and a larger amount for reads. This processing requires that the probe be able to recognize the commands being sent to the DIMM so that it can compute whether a given burst is a read or a write.

The clock used for state mode sampling of the DDR address/command bus is CK0 and #CK0. If the DDR controller does not drive these signals to DIMM slots that do not identify themselves as DDR memory then the analyzer will not be able to do state data capture on the address/command data or properly compute the analysis clock for state acquisition of DDR write and read data.  If the controller turns off the CK0/#CK0 signals to the DIMM slot containing the DDR Probe, then you have two options for capture of DDR data:

1) Override the controller programming or bring the CK0/#CK0 clocks to the probed DIMM slot from another slot. This will allow full functionality of the probe (i.e. acquisition of read AND write bursts in a single trace)

2) Set the Probe configuration switches (read and write switches should be in the off position) to pass the DQS0 clock directly to the analyzer. EyeFinder can then be used to calibrate the analyzer for capture of either read OR write bursts, but not both. To switch from one burst type to the other, the analyzer must be recalibrated using EyeFinder. This also places constraints on the stimulus used while EyeFinder is run. Specifically, during calibration for reads the stimulus must ONLY do read bursts, and vice versa for writes. This mode assumes that DQS0 is available to all DIMMS (even ones with no memory loaded). Inverse assembly is used only for state mode data. This means that CK0/#CK0 must be active for inverse assembly. Timing mode will work whether the state clocks are available or not.

The DIMM select test points are located on the top part of the board and are labeled "CH15", "CH14", "CH13" to reflect the analyzer channels they are associated with. You should just solder wires directly into the thru hole for the test point you want to use. Each test point has a ground test point next to it so you can use twisted pair wires to improve signal integrity. The other end of the wire can be soldered to the appropriate DIMM select signal on the motherboard or on the appropriate DIMMS.

Q. Can I use the 16760A logic analyzer module with the FS1107 software?

A. At a minimum you will probably need 5 cards ( using time tags), depending on how fast your bus is going. Let's assume 266 MT/s. With 5 cards you will not be able to capture simultaneous reads/writes, simply because you would not have enough pods. If your system is runing at 266, the analyzer will need to run in 400 Mb/s mode which needs a pod pair for time tags ( that is why it goes to 5 cards). If you are only doing timing analysis you will need 4 cards. This setup also assumes 64 bit data bus. We recommend the 16753A - 16756A cards instead.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

Have a question you don't see answered? Contact Technical Support for a prompt answer.

FS2333 DDR1 SO-DIMM Analysis Probe

Q. Which SO-DIMMs does your FS2333 DDR Analysis Probe support?

A. The FS2333 supports the PC2700 module, a 200-pin, 167 MHz clock (333 MT/s data rate), 64-bit, Unbuffered Synchronous Double Date Rate (DDR) DRAM Small Outline Dual In-Line Memory Module (DDR SDRAM SO-DIMM). It also supports slowers versions that uses a 100 MHz (200 MT/s data rate) or a 133 MHz clock (266 MT/s data rate) DDR SDRAM SO-DIMM. Registered and non-registered SO-DIMMs are supported.

Q. How does the Agilent logic analyzer connect to the FS2333 DDR Analysis Probe?

A. The FS2333 attaches to the logic analyzer with Termination Adapters. Two are available. The FS1014 (Agilent E5378A) attaches to a 16753A thorugh 16756A or 16760A and the FS1015 (Agilent E5385A) attaches to a 16717, 16740 or 16750. The necessary impedance matching networks are included in the adapters. See Ordering Information for the correct quantities.

Q. Are there egress issues with the FS2333 DDR Analysis Probe?

A. No. The FS2333 comes with two different adapters (click on the photo to the right to see them). One of the adapters should allow the FS2333 to fit into any target system.

Q. What software is included with the FS2333 DDR Analysis Probe?

A. Files are included that automatically set up your Agilent logic analyzer for state or timing analysis mode and label all the signal names. Another file is the transactor, which translates the signals into bus transactions during state analysis.

Q. Does your probe get its power from my system?

A. No. All necessary power is supplied by the logic analyzer.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

Have a question you don't see answered? Contact Technical Support for a prompt answer.

FS2336 DDR1 400 DIMM Analysis Probe

Q. Which DIMMs does your FS2336 DDR Analysis Probe support?

A. The FS2336 supports registered and non-registered DIMMS. Both x4 and x8 SDRAMS are supported. The probe fits in a standard 184-pin DIMM socket.

Q. How does the Agilent logic analyzer connect to the FS2336 DDR Analysis Probe?

A. The FS2336 attaches to the logic analyzer with a Termination Adapter. Three are available. The Agilent E5378A attaches to a 16753A-756A, 16760A, or 16950A. The Agilent E5385A attaches to a 16717, 16740, 16750-752, or 16910-911. The FS1026 is similar to an E5378A and attaches to a 16753A-756A, 16760A, or 16950A, but makes a right angle turn at the connector. This one is recommended when you are probing next to an adjacent DIMM. The necessary impedance matching networks are included in the adapters.

Q. Why does the FS2336 take four logic analyzer cards when it only requires four termination adapters?

A. The FS2336 requires up to four logic analyzer cards depending on whether protocol analysis (double probed) or timing analysis is being used, and the type of logic analyzer card being used. A fifth card may be required if all signals must be observed simultaneously. The customer will need 4 cards/8 pod pairs/16 pods and 4 - E5378 or 4 - FS1026 termination adapters:
*2 cards/4 pod pairs/8 pods are needed for the data and command bus
*1 card/2 pod pairs consumed by the new internal double probing system (multiplexing) for data bus only
*1 card/ 1 pod pair consumed by Turbo Mode for the data bus

This totals 4 cards/7 pod pairs/14 pods used by this configuration

There is an optional 5th card + 1 termination adapter (using 1 pod pair for signals + 2nd pod pair for internal double probing system

PLEASE NOTE: using the FS2336 may require a 16700 operating system update. Please contact FuturePlus for details.

Why can't I use a 16750-752 class of logic analyzer module with the FS2336? The 16750-752 modules are spec'ed at 400 MT/s which is what the DDR400 bus operates at.

A. Good question. The FS2336 is supported at 400 MT/s with the 16753-756 because of the data valid requirements of the DDR400 bus. The DDR400 bus data valid window can be as low as 900 ps. The 16750-752 cards require a minimum of 1200 ps. The 16753-756 can operate as low as 800 ps. If your data valid window on your bus is higher than 1200 ps you may be able to use the 16750-752 cards. In this case you need to use the Agilent E5385A termination adapters, which may pose a mechanical interference problem. The FS1026 termination adapter was designed to work with the 16753-756 cards and makes a 90 degree bend at the probe, thus resolving the potential mechanical interference problem.

Q. Can the FS2336 perform Eye Scan measurements?

A. The FS2336 can do Eye Scan for Command activity clocked by CK0. If the target can generate just Read or Write activity, then a data strobe signal (DQS2, DQS7, or DQS17) can be used to clock EyeScan for the data signals.

Q. Does the FS2336 DDR Protocol Decoder display ECC? If so, what information is displayed?

A. Yes. The FS2336 Protocol Decoder displays the ECC bits along with the data. After the data is displayed we output CB=XX where XX is the value of the ECC bits in hex.

Q. What software is included with the FS2336 DDR Analysis Probe?

A. Files are included that automatically set up your Agilent logic analyzer for protocol decode or timing analysis mode and label all the signal names. Another file is the protocol decoder, which translates the signals into bus transactions.

Q. Does your probe get its power from my system?

A. No. All necessary power is supplied by the logic analyzer.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

Have a question you don't see answered? Contact Technical Support for a prompt answer.

FS2337 DDR2 667 SO-DIMM Analysis Probe

Q. Which SO-DIMMs does your FS2337 DDR2 SO-DIMM Analysis Probe support?

A.The FS2337 supports the PC2-4300 memory module, a 200-pin, 267 MHz clock (533 MT/s data rate), 64-bit wide, (Up to 72 bits with ECC) Unbuffered Synchronous Double Data Rate 2 (DDR2) DRAM Small Outline Dual In-Line Memory Module (DDR2 SDRAM SODIMMs). It also supports a slower verion, the PC2-3200, using 200 MHz clock (400 MT/s data rate) DDR2 SDRAMs SODIMM.

Q. Why does the FS2337 take four logic analyzer cards when it only requires four termination adapters?

A. The FS2337 requires up to four logic analyzer cards depending on whether protocol analysis (double probed) or timing analysis is being used, and the type of logic analyzer card being used. The customer will need 4 cards/8 pod pairs/16 pods and 4 - E5378A termination adapters:
* 2 cards/4 pod pairs/8 pods are needed for the data and command bus
* 1 card/2 pod pairs consumed by the new internal double probing system (multiplexing) for data bus only
* 1 card/ 1 pod pair consumed by Turbo Mode for the data bus

This totals 4 cards/7 pod pairs/14 pods used by this configuration

PLEASE NOTE: using the FS2337 may require a 16700 operating system update. Please contact FuturePlus for details.

Q. Why can't I use a 16750-752 class of logic analyzer module with the FS2337? The 16750-752 modules are spec'ed at 400 MT/s which is what the DDR2 bus operates at.

A. Good question. The FS2337 is supported at up to 667 MT/s with the 16753-756 because of the data valid requirements of the DDR2 bus. The DDR2 bus data valid window can be as low as 900 ps. The 16750-752 cards require a minimum of 1200 ps. The 16753-756 can operate as low as 800 ps. If your data valid window on your bus is higher than 1200 ps you may be able to use the 16750-752 cards.

Q. Can you guarantee the FS2337 will operate correctly in my system?

A. Another good question. Electrically, the DDR2 bus is extended a small amount in the design of the FS2337. Depending on the design of the system being tested, users may experience difficulties with this extension of the DDR2 bus. The passive logic analyzer termination presents a single electrical load on the DDR bus via low capacitance, high impedance terminators, and also provides a matched impedance to the logic analyzer. The analysis probe includes four logic analyzer connectors. Factors beyond the control of FuturePlus Systems that can have a significant effect on the performance of the whole DDR2 system include the type of memory controller, the target layout, the type of DIMM used, which DIMM socket is being probed, and which logic analyzer cards are being used. So, we cannot guarantee your success. We have made every effort to give you a product that has every chance of succeeding.

Q. Can the FS2337 perform Eye Scan measurements?

A. The FS2337 can do Eye Scan for Command activity clocked by CK0. If the target can generate just Read or Write activity, then a data strobe signal (DQS2, DQS7, or DQS17) can be used to clock EyeScan for the data signals.

Q. What software is included with the FS2337 DDR2 Analysis Probe?

A. Files are included that automatically set up the Agilent logic analyzer for state or timing analysis mode and label all the signal names. Another file contains the protocol decoder, which translates the data into memory protocol during state analysis.

Q. Does your probe get its power from my system?

A. No. All necessary power is supplied by the logic analyzer.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

Have a question you don't see answered? Contact Technical Support for a prompt answer.

FS2332 DDR2 DIMM Analysis Probe

Q. Which DIMMs does your FS2332 DDR2 Analysis Probe support?

A.The FS2332 supports the PC3200 module, a 240-pin, 200 MHz clock (400 MT/s data rate), 64-bit, Unbuffered Synchronous Double Date Rate (DDR) DRAM Dual In-Line Memory Module (DDR SDRAM DIMM). It also supports slower versions that use a 100 MHz (200 MT/s data rate) or a 133 MHz clock (266 MT/s data rate) DDR SDRAM DIMM. Registered and non-registered DIMMs are supported.

Q. Why does the FS2332 take four logic analyzer cards when it only requires four termination adapters?

A. The FS2332 requires up to four logic analyzer cards depending on whether protocol analysis (double probed) or timing analysis is being used, and the type of logic analyzer card being used. A fifth card may be required if all *DQS and SPD-EEPROM signals must be observed simultaneously. The customer will need 4 cards/8 pod pairs/16 pods and 4 - E5378A or 4 - FS1026 termination adapters:
* 2 cards/4 pod pairs/8 pods are needed for the data and command bus
* 1 card/2 pod pairs consumed by the new internal double probing system (multiplexing) for data bus only
* 1 card/ 1 pod pair consumed by Turbo Mode for the data bus

This totals 4 cards/7 pod pairs/14 pods used by this configuration

There is an optional 5th card + 1 termination adapter (using 1 pod pair for signals + 2nd pod pair for internal double probing system

PLEASE NOTE: using the FS2332 may require a 16700 operating system update. Please contact FuturePlus for details.

Q.What are RDIMM's and UDIMM's?

A. UDIMM is an unregistered DIMM and RDIMM is a Registered DIMM.  With registered DIMM's the Address/Command information go through buffers.  Registered DIMM's are usually used in servers; this allows the user to put more DIMMs on a motherboard than unregistered DIMMs, because the Address/command info go through buffers.  The buffers add a delay of 1 clock cycle between when the command is issued to when the data is valid for a read or write.  This delay can be compensated through the preferences.  The FS2332 supports both UDIMM's and RDIMM's

Q. Why can't I use a 16750-753 class of logic analyzer module with the FS2332? The 16750-753 modules are spec'ed at 400 MT/s which is what the DDR2 bus operates at.

Good question. The FS2332 is supported at up to 667 MT/s with the 16753-756 because of the data valid requirements of the DDR2 bus. The DDR2 bus data valid window can be as low as 900 ps. The 16750-752 cards require a minimum of 1200 ps. The 16753-756 can operate as low as 800 ps. If your data valid window on your bus is higher than 1200 ps you may be able to use the 16750-752 cards. In this case you need to use the E5385A termination adapters, which may pose a mechanical interference problem. The FS1026 termination adapter was designed to work with the 16753-756 cards and makes a 90 degree bend at the probe, thus resolving the potential mechanical interference problem.

Q. Can I use a 16760 logic analyzer module with the FS2332?

At this time we don't include an config file for it, but it would work. The 16760 has 2 pods per card. You will need to use 5 cards, because you need to attach 8 pods to the probe and then you will need 2 pods for turbo mode.  If you plan to do this, contact technical support and they will make a config file for you.

Q. Can you guarantee the FS2332 will operate correctly in my system?

A. Another good question. Electrically, the DDR2 bus is extended approximately 1.0 inch in etch length in the design of the FS2332. Depending on the design of the system being tested, users may experience difficulties with this extension of the DDR2 bus. The passive logic analyzer termination presents a single electrical load on the DDR bus via low capacitance, high impedance terminators, and also provides a matched impedance to the logic analyzer. The analysis probe includes four logic analyzer connectors. Factors beyond the control of FuturePlus Systems that can have a significant effect on the performance of the whole DDR2 system include the type of memory controller, the target layout, the type of DIMM used, which DIMM socket is being probed, and which logic analyzer cards are being used. So, we cannot guarantee your success. We have made every effort to give you a product that has every chance of succeeding.

Q. Can the FS2332 perform Eye Scan measurements?

A. The FS2332 can do Eye Scan for Command activity clocked by CK0. If the target can generate just Read or Write activity, then a data strobe signal (DQS2, DQS7, or DQS17) can be used to clock EyeScan for the data signals.

Q. Does the FS2332 DDR Protocol Decoder display ECC? If so, what information is displayed?

A. Yes. The FS2332 Protocol Decoder displays the ECC bits along with the data. After the data is displayed we output CB=XX where XX is the value of the ECC bits in hex.

Q. What software is included with the FS2332 DDR2 Analysis Probe?

A. Files are included that automatically set up the Agilent logic analyzer for state or timing analysis mode and label all the signal names. Another file contains the protocol decode, which translates the data into memory protocol during state analysis.

Q. Does your probe get its power from my system?

A. No. All necessary power is supplied by the logic analyzer.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

Have a question you don't see answered? Contact Technical Support for a prompt answer.

FS2359B DDR3 1600 SO-DIMM Interposer
Tektronic Logic Analyzer Support

Q. Which SO-DIMMs does the FS2359B DDR3 SO-DIMM interposer support?

A.  The FS2359 supports a 204-pin, 800 MHz clock (1600 MT/s data rate), 64-bit, Unbuffered Synchronous Double Date Rate (DDR) DRAM Small Outline Dual In-Line Memory Module (DDR SDRAM SO-DIMM). Registered and non-registered SO-DIMM's are also supported.

Q. Can you guarantee the FS2359B will operate correctly in my system?

A. A good question. Electrically, the FS2359B extends the DDR3 bus approximately 1.0 inch in etch length. FuturePlus has carefully simulated and designed the FS2359B to work in your system. Factors that can have a significant effect on the performance of the whole DDR3 system include the type of memory controller, the target layout, the type of SO-DIMM used, and which SO-DIMM socket is being probed. All users are given 30 days to qualify the FS2359B in their system.

Q. How does the FS2358B require only 2 logic analyzer modules for 1600 operation?

A. The FS2358B hardware and software takes advantage of the unique multiplexing feature of the TLA7BB4 modules, thus reducing the module requirements in half.

Q. Does the FS2359B product provide for automated sample point setting?

A. Yes. The FuturePlus Sample Point Finder software provides for automated sample point settings, both voltage and time.

Q. Does the FS2359B DDR Protocol Decoder display ECC?

A. Yes

Q. What software is included with the FS2359B DDR3 interposer?

A. The protocol disassembler and the setup files with Sample Point Finder are included for 1333 operation. For 1600 operation, you need to order the optional FS1183 Support Package. Command performance analysis software is also provided.

Q. Does your probe get its power from my system?

A. No. The FS2359B requires external power and a DC power supply is included.

Q. How do I find out what are the latest versions of Tektronix logic analyzer operating software?

A. Contact your nearest Tektronix Call Center.

Q. How do I know which Tektronix logic analyzer is best for my needs?

A. Click here.

Have a question you don't see answered? Contact Technical Support for a prompt answer.

FS2354 DDR3 1600 SO-DIMM Analysis Probe
Agilent Logic Analyzer Support

Q. Which SO-DIMMs does the FS2354 DDR3 SO-DIMM interposer support?

A.  The FS2354 supports a 204-pin, 667 MHz clock (1600 MT/s data rate), 64-bit, Unbuffered Synchronous Double Date Rate (DDR) DRAM Small Outline Dual In-Line Memory Module (DDR SDRAM SO-DIMM). Registered and non-registered SO-DIMM's are supported.

Q. Can you guarantee the FS2354 will operate correctly in my system?

A. A good question. Electrically, the FS2354 extends the DDR3 bus approximately 1.0 inch in etch length. FuturePlus has carefully simulated and designed the FS2354 to work in your system. Factors that can have a significant effect on the performance of the whole DDR3 system include the type of memory controller, the target layout, the type of DIMM used, and which DIMM socket is being probed. All users are given 30 days to qualify the FS2354 in their system.

Q. How does the FS2354 set sampling points for read and write traffic?

A. The FS2354 uses the Agilent EyeScan feature to do this.

Q. Does the FS2354 DDR Protocol Decoder display ECC?

A. Yes

Q. What software is included with the FS2354 DDR3 interposer?

A. The protocol decoder and the logic analyzer config files are included.

Q. Does your probe get its power from my system?

A. No. The FS2354 does not have any active circuitry.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

Have a question you don't see answered? Contact Technical Support for a prompt answer.

FS2358B DDR3 1333/1600/1867 DIMM Interposer
Tektronix Logic Analyzer Support

Q. Which DIMMs does the FS2358B DDR3 interposer support?

A.  The FS2358B supports a 240-pin, 667 MHz clock (1333 MT/s data rate), 64-bit, Registered or Unbuffered Synchronous Double Date Rate (DDR) DRAM Dual In-Line Memory Module (DDR SDRAM DIMM). 800 MHz clock (1600 MT/s data rate) DIMM's or 933 MHz clock (1867 MT/s data rate) DIMM's are supported by adding the optional FS1181 Support Package.

Q. Can you guarantee the FS2358B will operate correctly in my system?

A. A good question. Electrically, the FS2358B extends the DDR3 bus approximately 1.0 inch in etch length. FuturePlus has carefully simulated and designed the FS2358B to work in your system. Factors that can have a significant effect on the performance of the whole DDR3 system include the type of memory controller, the target layout, the type of DIMM used, and which DIMM socket is being probed. All users are given 30 days to qualify the FS2358B in their system.

Q. How does the FS2358B require only 2 logic analyzer modules for 1600+ operation?

A. The FS2358B hardware and software takes advantage of the unique multiplexing feature of the TLA7BB4 modules, thus cutting the module requirements in half.

Q. Does the FS2358B product provide for automated sample point setting?

A. Yes. The FuturePlus Sample Point Finder software provides for automated sample point settings, both voltage and time.

Q. Does the FS2358B DDR Protocol Decoder display ECC?

A. Yes.

Q. What software is included with the FS2358B DDR3 interposer?

A. The protocol disassembler and the setup files with Sample Point Finder are included for 1333 operation. For 1600 and 1867 operation, you need to order the optional FS1181 Support Package. Command performance analysis software is also provided.

Q. Does your probe get its power from my system?

A. No. The FS2358B requires external power and a DC power supply is included.

Q. How do I find out what are the latest versions of Tektronix logic analyzer operating software?

A. Contact your nearest Tektronix Call Center.

Q. How do I know which Tektronix logic analyzer is best for my needs?

A. Click here.

Have a question you don't see answered? Contact Technical Support for a prompt answer.

FS2351 DDR3 1333 DIMM Analysis Probe
Agilent Logic Analyzer Support

Q. Which DIMMs does the FS2351 DDR3 Analysis Probe support?

A.  The FS2351 supports a 240-pin, 667 MHz clock (1333 MT/s data rate), 64-bit, Unbuffered Synchronous Double Date Rate (DDR) DRAM Dual In-Line Memory Module (DDR SDRAM DIMM).

Q. Why does the FS2351 require seven logic analyzer cards?

A. The FS2351 requires seven logic analyzer cards for protocol analysis or three logic analyzer cards for timing analysis. The FS2351 requires that the 16950B card be in 1067 Mb/s mode, which allows only 2 pods per card for use. The first card is for ADDR/Cmd signals, cards 2-4 are for WRITE Data, and cards 5-7 are used for READ data. Since the 16900 and 16902 have six slots, this system requires two logic analysis frames. We recommend using 16900 operating system version 3.50 or higher with the FS2351. You may also use the 16753-756 cards. All seven must be the same model number. UPDATE - With the new 16962A card, you only need four for 1333 MT/s analysis.

Q. When do I need to use the new 16950B card with the FS2351? What's the difference from the 16950A/B? Can I use them together?

A. The 16950B has a supported state clock speed of 667 MHz in turbo mode, higher than the 600 MHz of the 16950A. The 16950B also has a smaller minimum data valid window requirement, 550 vs. 600 pS. Lastly, the 16950B has a state data rate speed of 1067 Mb/s, higher than the 16950A's 800 Mb/s. These 16950B features are required by the DDR3 bus running at 1067 MT/s. The 16950A and 16950B can NOT be melded together, the SW will not allow the merger. The 16950A can be melded with 16753/54/55/56A modules.  When melded, the set takes on the lowest memory depth of the modules in the set. The 16951B is the new deep memory (256M) module.  The 16950B and 16951B can NOT be melded.  

Q. Can you guarantee the FS2351 will operate correctly in my system?

A. Another good question. Electrically, the DDR3 bus is extended approximately 1.0 inch in etch length in the design of the FS2351. Depending on the design of the system being tested, users may experience difficulties with this extension of the DDR3 bus. The passive logic analyzer termination presents a single electrical load on the DDR bus via low capacitance, high impedance terminators, and also provides a matched impedance to the logic analyzer. The analysis probe includes seven cables that connect to the logic analyzer modules. Factors beyond the control of FuturePlus Systems that can have a significant effect on the performance of the whole DDR3 system include the type of memory controller, the target layout, the type of DIMM used, which DIMM socket is being probed, and which logic analyzer cards are being used. So, we cannot guarantee your success. We have made every effort to give you a product that has every chance of succeeding.

Q. Can the FS2351 perform Eye Scan measurements?

A. Yes. The FS2351 can do Eye Scan for Command activity clocked by CK0, Chip Select qualification may be required. If the target can generate just Read or Write activity, then a data strobe signal (DQS2, DQS7, or DQS17) can be used to clock Eye Scan for the data signals.

Q. Does the FS2351 DDR Protocol Decoder display ECC?

A. The ECC bits are available on Header 14. However, viewing them may require an additional logic analysis module and modification of existing configuration files.

Q. What software is included with the FS2351 DDR3 Analysis Probe?

A. Files are included that automatically set up the Agilent logic analyzer for state or timing analysis mode and label all the signal names. Another file contains the protocol decoder, which translates the data into memory protocol during state analysis. The DDR Protocol Checker and Performance Analysis software provides measurements of the data window eye width on a bit by bit basis across all Timing Zoom data in the trace file; additionally it identifies those signals with the smallest eye width.

Q. Does the FS2351 include the Transaction Viewer software?

A. No. The FS2351 requires two 16900 or 16902 frames. The Transaction Viewer software has only been designed for one frame at this time.

Q. Does your probe get its power from my system?

A. No. The FS2351 does not have any active circuitry.

Q. When I use my FS2351 in my target, it doesn't boot. Is this a known problem?

A. Possibly. JEDEC changed the function of pin #119 from ground to SA2 after the FS2351 was designed. If your target is using pin #119 as SA2, this will cause a boot problem when the FS2351 is installed. This is simple fix, please contact the factory for instructions on returning it and we will be happy to fix it.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

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FS2352 DDR3 1867 DIMM Interposer
Agilent Logic Analyzer Support

Q. Which DIMMs does the FS2352 DDR3 Analysis Probe support?

A.  The FS2352 supports a 240-pin, 64-bit, Unbuffered or Registered Synchronous Double Date Rate (DDR) DRAM Dual In-Line Memory Module (DDR SDRAM DIMM). Clock rates up to 933 MHz (1867 MT/s) DIMM's are supported by the standard product.

Q. Can you guarantee the FS2352 will operate correctly in my system?

A. A good question. Note: Electrically, the FS2352 extends the DDR3 bus approximately 1.0 inch in etch length. FuturePlus has carefully simulated and designed the FS2352 to work in your system. Factors that can have a significant effect on the performance of the whole DDR3 system include the type of memory controller, the target layout, the type of DIMM used, and which DIMM socket is being probed. All users are given 30 days to qualify the FS2352 in their system.

Q. Can the FS2352 perform Eye Scan measurements?

A. Yes. The FS2352 can do Eye Scan for Command activity clocked by CK0, Chip Select qualification may be required. If the target can generate just Read or Write activity, then a data strobe signal (DQS2, DQS7, or DQS17) can be used to clock Eye Scan for the data signals.

Q. Does the FS2352 DDR Protocol Decoder display ECC?

A. The ECC bits are available on Header 14. However, viewing them may require an additional logic analysis module and modification of existing configuration files.

Q. What software is included with the FS2352 DDR3 Analysis Probe?

A. Files are included that automatically set up the Agilent logic analyzer for state or timing analysis mode and label all the signal names. Another file contains the protocol decoder, which translates the data into memory protocol during state analysis. The DDR Protocol Checker and Performance Analysis software provides measurements of the data window eye width on a bit by bit basis across all Timing Zoom data in the trace file; additionally it identifies those signals with the smallest eye width.

Q. Does your probe get its power from my system?

A. No. The FS2352 does not have any active circuitry.

Q. How do I find out what are the latest versions of Agilent logic analyzer operating software?

A. Contact your nearest Agilent Call Center.

Q. How do I know which Agilent logic analyzer is best for my needs?

A. Click here.

Have a question you don't see answered? Contact Technical Support for a prompt answer.